Publications

Chen, Y., H. Li, C. K. Koh, J. Li, K. Roy, G. Sun, and Y. Xie. “Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.” IEEE Transactions on Very Large Scale Integration VLSI Systems 18, no. 11 (January 1, 2010): 1621–24. https://doi.org/10.1109/TVLSI.2009.2026280.

Sun, Z., H. Li, Y. Chen, and X. Wang. “Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 432–37, 2010. https://doi.org/10.1109/ICCAD.2010.5653720.

Sun, G., Y. Joo, Y. Chen, D. Niu, Y. Xie, and H. Li. “A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.” In Proceedings - International Symposium on High-Performance Computer Architecture, 2010. https://doi.org/10.1109/hpca.2010.5416650.

Xu, W., T. Zhang, and Y. Chen. “Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search Speed.” IEEE Transactions on Very Large Scale Integration VLSI Systems 18, no. 1 (January 1, 2010): 66–74. https://doi.org/10.1109/TVLSI.2008.2007735.

Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “The salvage cache: A fault-tolerant cache architecture for next-generation memory technologies.” In Proceedings IEEE International Conference on Computer Design VLSI in Computers and Processors, 268–74, 2009. https://doi.org/10.1109/ICCD.2009.5413145.

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” IEEE Transactions on Very Large Scale Integration VLSI Systems 17, no. 12 (December 1, 2009): 1749–52. https://doi.org/10.1109/TVLSI.2008.2007843.

Chen, Y., and X. Wang. “Compact modeling and corner analysis of spintronic memristor.” In 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, 7–12, 2009. https://doi.org/10.1109/NANOARCH.2009.5226363.

Hai, L., and C. Yiran. “An overview of non-volatile memory technology and the implication for tools and architectures.” In Proceedings Design Automation and Test in Europe Date, 731–36, 2009.

Li, H., H. Xi, Y. Chen, J. Stricklin, X. Wang, and T. Zhang. “Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration.” In Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2009, 217–22, 2009. https://doi.org/10.1109/ISVLSI.2009.17.

Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.

Xi, H., X. Wang, Y. Chen, and P. J. Ryan. “Ordering of magnetic nanoparticles in bilayer structures.” Journal of Physics D: Applied Physics 42, no. 1 (April 8, 2009). https://doi.org/10.1088/0022-3727/42/1/015006.

Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” IEEE Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.

Sun, G., X. Dong, Y. Xie, J. Li, and Y. Chen. “A novel architecture of the 3D stacked MRAM L2 Cache for CMPs.” In Proceedings International Symposium on High Performance Computer Architecture, 239–49, 2009. https://doi.org/10.1109/HPCA.2009.4798259.

Xu, W., Y. Chen, X. Wang, and T. Zhang. “Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.” In Proceedings Design Automation Conference, 87–90, 2009. https://doi.org/10.1145/1629911.1629936.

Xu, W., T. Zhang, and Y. Chen. “Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.” In Proceedings IEEE International Symposium on Circuits and Systems, 1898–1901, 2008. https://doi.org/10.1109/ISCAS.2008.4541813.

Dong, X., X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.” In Proceedings Design Automation Conference, 554–59, 2008. https://doi.org/10.1109/DAC.2008.4555878.

Chen, Y., X. Wang, H. Li, H. Liu, and D. V. Dimitrov. “Design margin exploration of Spin-Torque Transfer RAM (SPRAM).” In Proceedings of the 9th International Symposium on Quality Electronic Design Isqed 2008, 684–90, 2008. https://doi.org/10.1109/ISQED.2008.4479820.

Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.

Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” IEEE Transactions on Magnetics 44, no. 11 PART 2 (January 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.

Chen, Yiran, Xiaobin Wang, Hai Li, Harry Liu, and Dimitar V. Dimitrov. “Design margin exploration of spin-torque transfer RAM (SPRAM).” In ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 684–90. IEEE COMPUTER SOC, 2008. https://doi.org/10.1109/ISQED.2008.140.

Chen, Y., H. Li, J. Li, and C. K. Koh. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” In Proceedings of the International Symposium on Low Power Electronics and Design, 195–200, 2007. https://doi.org/10.1145/1283780.1283822.

Wong, W. F., C. K. Kon, Y. Chen, and H. Li. “VOSCH: Voltage scaled cache hierarchies.” In 2007 IEEE International Conference on Computer Design Iccd 2007, 496–503, 2007. https://doi.org/10.1109/ICCD.2007.4601944.

Li, H., C. K. Koh, V. Balakrishnan, and Y. Chen. “Statistical timing analysis considering spatial correlations.” In Proceedings Eighth International Symposium on Quality Electronic Design Isqed 2007, 102–7, 2007. https://doi.org/10.1109/ISQED.2007.149.

Li, H., Y. Chen, K. Roy, and C. K. Koh. “SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 2006:158–63, 2006.

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 115–18, 2005.