Publications

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 115–18, 2005.

Kang, D., Y. Chen, and K. Roy. “Power supply noise-aware scheduling and allocation for DSP synthesis.” In Proceedings International Symposium on Quality Electronic Design Isqed, 48–53, 2005. https://doi.org/10.1109/ISQED.2005.97.

Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” IEEE Transactions on Very Large Scale Integration VLSI Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.

Lam, W. C. D., J. Jain, C. K. Koh, V. Balakrishnan, and Y. Chen. “Statistical based link insertion for robust clock network design.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 2005:588–91, 2005. https://doi.org/10.1109/ICCAD.2005.1560134.

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Proceedings of the Custom Integrated Circuits Conference, 2005:775–78, 2005. https://doi.org/10.1109/CICC.2005.1568783.

Chen, Y., K. Roy, and C. K. Koh. “Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors.” IEEE Transactions on Very Large Scale Integration VLSI Systems 13, no. 1 (January 1, 2005): 75–85. https://doi.org/10.1109/TVLSI.2004.840404.

Chen, Y. R., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 775–78. IEEE, 2005.

Chen, Y., K. Roy, and C. K. Koh. “Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 894–99, 2004.

Li, H., S. Bhunia, Y. Chen, K. Roy, and T. N. Vijaykumar. “DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design.” IEEE Transactions on Very Large Scale Integration VLSI Systems 12, no. 3 (March 1, 2004): 245–54. https://doi.org/10.1109/TVLSI.2004.824307.

Agarwal, A., H. Li, and K. Roy. “A single-Vt low-leakage gated-ground cache for deep submicron.” IEEE Journal of Solid State Circuits 38, no. 2 (February 1, 2003): 319–28. https://doi.org/10.1109/JSSC.2002.807414.

Chen, Y., K. Roy, and C. K. Koh. “Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.” In Proceedings of the International Symposium on Low Power Electronics and Design, 2003-January:229–34, 2003. https://doi.org/10.1109/LPE.2003.1231867.

Li, H., C. Y. Cher, T. N. Vijaykumar, and K. Roy. “VSV: L2-miss-driven variable supply-voltage scaling for low power.” In Proceedings of the Annual International Symposium on Microarchitecture Micro, 2003-January:19–28, 2003. https://doi.org/10.1109/MICRO.2003.1253180.

Chen, Y., K. Roy, and C. K. Koh. “Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors.” In Proceedings of the International Symposium on Low Power Electronics and Design, 229–34, 2003. https://doi.org/10.1145/871506.871563.

Li, H., S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy. “Deterministic clock gating for microprocessor power reduction.” In Proceedings International Symposium on High Performance Computer Architecture, 12:113–22, 2003. https://doi.org/10.1109/HPCA.2003.1183529.

Chen, Y., V. Balakrishnan, C. K. Koh, and K. Roy. “Model reduction in the time-domain using Laguerre polynomials and Krylov methods.” In Proceedings Design Automation and Test in Europe Date, 931–36, 2002. https://doi.org/10.1109/DATE.2002.998411.

Agarwal, A., H. Li, and K. Roy. “DRG-Cache: A data retention gated-ground cache for low power.” In Proceedings Design Automation Conference, 473–78, 2002. https://doi.org/10.1109/dac.2002.1012671.

Bhunia, S., H. Li, and K. Roy. “A high performance IDDQ testable cache for scaled CMOS technologies.” In Proceedings of the Asian Test Symposium, 2002-January:157–62, 2002. https://doi.org/10.1109/ATS.2002.1181704.