Publications

Liu, B., Y. Chen, B. Wysocki, and T. Huang. “The circuit realization of a neuromorphic computing system with memristor-based synapse design.” In Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 7663 LNCS:357–65, 2012. https://doi.org/10.1007/978-3-642-34475-6_43.

Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” IEEE Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.

Zhang, Y., W. Wen, and Y. Chen. “The prospect of STT-RAM scaling from readability perspective.” IEEE Transactions on Magnetics 48, no. 11 (October 29, 2012): 3035–38. https://doi.org/10.1109/TMAG.2012.2203589.

Bi, X., H. Li, and J. J. Kim. “Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design.” In Proceedings 2012 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2012, 374–79, 2012. https://doi.org/10.1109/ISVLSI.2012.56.

Shao, Z., Y. Liu, Y. Chen, and T. Li. “Utilizing PCM for energy optimization in embedded systems.” In Proceedings 2012 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2012, 398–403, 2012. https://doi.org/10.1109/ISVLSI.2012.81.

Chen, Y. C., H. Li, and W. Zhang. “A novel peripheral circuit for RRAM-based LUT.” In Iscas 2012 2012 IEEE International Symposium on Circuits and Systems, 1811–14, 2012. https://doi.org/10.1109/ISCAS.2012.6271619.

Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” IEEE Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.

Sun, Z., H. Li, and W. Wu. “A dual-mode architecture for fast-switching STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 45–50, 2012. https://doi.org/10.1145/2333660.2333673.

Sun, Z., X. Bi, and H. Li. “Process variation aware data management for STT-RAM cache design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 179–84, 2012. https://doi.org/10.1145/2333660.2333706.

Sun, G., Y. Zhang, Y. Wang, and Y. Chen. “Improving energy efficiency of write-asymmetric memories by log style write.” In Proceedings of the International Symposium on Low Power Electronics and Design, 173–78, 2012. https://doi.org/10.1145/2333660.2333705.

Li, Y., Y. Chen, and A. K. Jones. “A software approach for combating asymmetries of non-volatile memories.” In Proceedings of the International Symposium on Low Power Electronics and Design, 191–96, 2012. https://doi.org/10.1145/2333660.2333708.

Zhang, Y., W. Wen, and Y. Chen. “STT-Ram cell design considering MTJ asymmetric switching.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400073.

Li, H. H., and Z. Sun. “Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400085.

Hu, M., H. Li, Q. Wu, G. S. Rose, and Y. Chen. “Memristor crossbar based hardware realization of BSB recall function.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252563.

Wang, H., H. Li, and R. E. Pino. “Memristor-based synapse design and training scheme for neuromorphic computing architecture.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252577.

Wen, W., Y. Zhang, Y. Chen, Y. Wang, and Y. Xie. “PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method.” In Proceedings Design Automation Conference, 1191–96, 2012. https://doi.org/10.1145/2228360.2228580.

Chen, X., J. Zheng, Y. Chen, M. Zhao, and C. J. Xue. “Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.” In Proceedings Design Automation Conference, 1000–1005, 2012. https://doi.org/10.1145/2228360.2228540.

Pino, R. E., H. Li, Y. Chen, M. Hu, and B. Liu. “Statistical memristor modeling and case study in neuromorphic computing.” In Proceedings Design Automation Conference, 585–90, 2012. https://doi.org/10.1145/2228360.2228466.

Hu, M., H. Li, Q. Wu, and G. S. Rose. “Hardware realization of BSB recall function using memristor crossbar arrays.” In Proceedings Design Automation Conference, 498–503, 2012. https://doi.org/10.1145/2228360.2228448.

Li, H., M. Hu, and R. Pino. “Statistical Memristor Model and Its Applications in Neuromorphic Computing.” In Advances in Neuromorphic Memristor Science and Applications, edited by R. Kozma, R. Pino, and G. Pazienza. Springer Science & Business Media, 2012.

Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” ACM Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.

Bi, X., C. Zhang, H. Li, Y. Chen, and R. E. Pino. “Spintronic memristor based temperature sensor design with CMOS current reference.” In Proceedings Design Automation and Test in Europe Date, 1301–6, 2012.

Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Architecting a common-source-line array for bipolar non-volatile memory devices.” In Proceedings Design Automation and Test in Europe Date, 1451–54, 2012.

Zhang, Y., X. Wang, Y. Li, A. K. Jones, and Y. Chen. “Asymmetry of MTJ switching and its implication to STT-RAM designs.” In Proceedings Design Automation and Test in Europe Date, 1313–18, 2012.

Chen, X., J. Zeng, Y. Chen, W. Zhang, and H. Li. “Fine-grained dynamic voltage scaling on OLED display.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 807–12, 2012. https://doi.org/10.1109/ASPDAC.2012.6165066.