Publications

Zhang, C., G. Sun, P. Li, T. Wang, D. Niu, and Y. Chen. “SBAC: A statistics based cache bypassing method for asymmetric-access caches.” In Proceedings of the International Symposium on Low Power Electronics and Design, 345–50, 2014. https://doi.org/10.1145/2627369.2627611.

Park, E., S. Yoo, S. Lee, and H. Li. “Accelerating graph computation with racetrack memory and pointer-assisted graph representation.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.172.

Chen, X., K. W. Nixon, H. Zhou, Y. Liu, and Y. Chen. “FingerShadow: An OLED power optimization based on smartphone touch interactions.” In 6th Workshop on Power Aware Computing and Systems Hotpower 2014, 2014.

Wang, Y., B. Li, R. Luo, Y. Chen, N. Xu, and H. Yang. “Energy efficient neural networks for big data analytics.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.358.

Sun, G., Y. Joo, Y. Chen, and Y. Xie. “A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement.” In Emerging Memory Technologies Design Architecture and Applications, 9781441995513:51–77, 2014. https://doi.org/10.1007/978-1-4419-9551-3_3.

Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “Exploration of GPGPU register file architecture using domain-wall-shift- write based racetrack memory.” In Proceedings Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2593137.

Wen, W., Y. Zhang, M. Mao, and Y. Chen. “State-restrict MLC stt-ram designs for high-reliable high-performance memory system.” In Proceedings Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2593220.

Sun, G., X. Dong, Y. Chen, and Y. Xie. “An energy-efficient 3D stacked STT-RAM cache architecture for CMPs.” In Emerging Memory Technologies Design Architecture and Applications, 9781441995513:145–67, 2014. https://doi.org/10.1007/978-1-4419-9551-3_6.

Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A new field-assisted access scheme of STT-RAM with self-reference capability.” In Proceedings Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2593075.

Chen, L., C. Li, T. Huang, Y. Chen, S. Wen, and J. Qi. “A synapse memristor model with forgetting effect.” Physics Letters Section A General Atomic and Solid State Physics 377, no. 45–48 (December 17, 2013): 3260–65. https://doi.org/10.1016/j.physleta.2013.10.024.

Li, B., Y. Shan, M. Hu, Y. Wang, Y. Chen, and H. Yang. “Memristor-based approximated computation.” In Proceedings of the International Symposium on Low Power Electronics and Design, 242–47, 2013. https://doi.org/10.1109/ISLPED.2013.6629302.

Wang, J., Y. Tim, W. F. Wong, and H. H. Li. “A practical low-power memristor-based analog neural branch predictor.” In Proceedings of the International Symposium on Low Power Electronics and Design, 175–80, 2013. https://doi.org/10.1109/ISLPED.2013.6629290.

Zhang, Y., I. Bayram, Y. Wang, H. Li, and Y. Chen. “ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 9–16, 2013. https://doi.org/10.1109/ICCAD.2013.6691091.

Jones, A. K., Y. Chen, W. O. Collinge, H. Xu, L. A. Schaefer, A. E. Landis, and M. M. Bilec. “Considering fabrication in sustainable computing.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 206–10, 2013. https://doi.org/10.1109/ICCAD.2013.6691120.

Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.

Wen, W., M. Mao, X. Zhu, S. H. Kang, D. Wang, and Y. Chen. “CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 1–8, 2013. https://doi.org/10.1109/ICCAD.2013.6691090.

Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.

Li, J., L. Shi, Q. Li, C. J. Xue, Y. Chen, Y. Xu, and W. Wang. “Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.” ACM Transactions on Design Automation of Electronic Systems 19, no. 1 (December 1, 2013). https://doi.org/10.1145/2534393.

Ji, F., H. H. Li, B. Wysocki, C. Thiem, and N. McDonald. “Memristor-based synapse design and a case study in reconfigurable systems.” In Proceedings of the International Joint Conference on Neural Networks, 2013. https://doi.org/10.1109/IJCNN.2013.6706776.

Wen, Shiping, Gang Bao, Zhigang Zeng, Yiran Chen, and Tingwen Huang. “Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays.” Neural Networks : The Official Journal of the International Neural Network Society 48 (December 2013): 195–203. https://doi.org/10.1016/j.neunet.2013.10.001.

Chen, Q., Q. Qiu, H. Li, and Q. Wu. “A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 202–5, 2013. https://doi.org/10.1109/ICCAD.2013.6691119.

Chen, Z., L. Zhang, X. Bi, and H. Li. “A pseudo-weighted sensing scheme for memristor based cross-point memory.” In Proceedings of the 2013 IEEE ACM International Symposium on Nanoscale Architectures Nanoarch 2013, 38–39, 2013. https://doi.org/10.1109/NanoArch.2013.6623039.

Li, Hong-jun, Zheng-guang Xie, and Wei Hu. “An image compression method using sparse representation and grey relation.” In Proceedings of 2013 IEEE International Conference on Grey Systems and Intelligent Services (GSIS), 53–56. IEEE, 2013. https://doi.org/10.1109/gsis.2013.6714741.

Wen, S., Z. Zeng, T. Huang, and Y. Chen. “Fuzzy modeling and synchronization of different memristor-based chaotic circuits.” Physics Letters Section A General Atomic and Solid State Physics 377, no. 34–36 (November 1, 2013): 2016–21. https://doi.org/10.1016/j.physleta.2013.05.046.

Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” ACM Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.