Centaur: A Bio-inspired Ultra Low-Power Hybrid Embedded Computing Engine Beyond One TeraFlops/Watt
The objective of the research is to innovate an embedded computing engine named “Centaur” to achieve ultra-high power efficiency by adopting the bio-inspired computation model and the advanced memristor technology. Creative applications of critical importance to nowadays mobile and embedded systems by taking the full advantages of Centaur, including pattern recognition and video and image processing, will be also explored. The research can benefit the embedded system community by the revolutions in computing architecture and hardware design for functional variety, power-efficiency, and cost. The results can further benefit the semiconductor and neuromorphic societies at large by stimulating the interaction between the advances in device engineering and computing models.
An Adaptive Information Processing System Resilient to Device Variations and Noises
The aggressive technology scaling imposes severe reliability challenges on present-day VLSI designs, e.g., the probabilistic behaviors of nano-scale circuitry due to process variations. Logic gates and memory cells also turn to be highly vulnerable to radiation-induced soft-errors due to the limited electrical charge stored on the internal capacitance. This project aims at a comprehensive solution set combating the statistical properties and intermittent failures incurred by the technology scaling in computing systems. In contrast to many existing approaches that focus on circuit and structural enhancements, our project offers an adaptive information processing VLSI system with significant revolutions across the levels of device, circuit, architecture and algorithm.
NeoNexus: The Next-generation Information Processing System across Digital and Neuromorphic Computing Domains
The explosion of “big data” applications imposes severe challenges of data processing speed and scalability on traditional computer systems. The performance of traditional Von Neumann machines is greatly hindered by the increasing performance gap between CPU and memory, motivating the active research on new or alternative computing architectures. By imitating brain’s naturally massive parallel architecture with closely coupled memory and computing as well as the unique analog domain operations, neuromorphic computing systems are anticipated to deliver superior speed for applications in image recognition and natural language understanding. The objective of this research is to establish the fundamental framework and design methodology for NeoNexus — the next-generation information processing system inspired by human neocortex. It integrates neuromorphic computing accelerators with conventional computing resources by leveraging large scale inference-based data processing and computing acceleration technique atop memristor crossbar arrays. The software-hardware co-design platform will be developed to address the various design challenges.
The Design of Neuromorphic Controller System Built with Memristor Crossbars
In the development history of microprocessors, although computing efficiency of solid state circuits keeps improving by following technology scaling, the data transportation efficiency between CPU cores and storage systems continue drifting down and starts dominating the energy consumption of the entire system. This phenomenon is referred to as the “memory wall”. The neuromorphic computing inspired by the working mechanism of human brains effectively reduces the data communication cost and consequently, achieves very high computation efficiency. However, neuromorphic systems, such as cortical processor, require very high connectivity and flexible reconfigurability, which commonly consumes a large volume of memory and computing resources, incurring high design complexity and hardware cost in conventional CMOS implementation. The objective of the project is to investigate the neuromorphic computing systems built with the emerging memristor technology. A neuromorphic computing controller integrated with real memristor crossbar array(s) will be developed and demonstrated at the end of the project.