Publications

Chen, Y. C., W. Wang, H. Li, and W. Zhang. “Non-volatile 3D stacking RRAM-based FPGA.” In Proceedings 22nd International Conference on Field Programmable Logic and Applications Fpl 2012, 367–72, 2012. https://doi.org/10.1109/FPL.2012.6339206.

Zhang, Y., L. Zhang, W. Wen, G. Sun, and Y. Chen. “Multi-level cell STT-RAM: Is it realistic or just a dream?” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 526–32, 2012.

Chen, Y., X. Chen, M. Zhao, and C. J. Xue. “Mobile devices user-The subscriber and also the publisher of real-time OLED display power management plan.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 687–90, 2012.

Chen, Y. C., W. Wang, W. Zhang, and H. Li. “uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.” In FPT 2012 - 2012 International Conference on Field-Programmable Technology, 80–86, 2012. https://doi.org/10.1109/FPT.2012.6412116.

Li, Y., Y. Zhang, Y. Chen, and A. K. Jones. “Combating write penalties using software dispatch for on-chip MRAM integration.” IEEE Embedded Systems Letters 4, no. 4 (December 1, 2012): 82–85. https://doi.org/10.1109/LES.2012.2216253.

Li, H., Z. Sun, X. Bi, and B. Wysocki. “Spintronic devices: From memory to memristor.” In ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, 2012. https://doi.org/10.1109/ICSICT.2012.6467793.

Liu, B., Y. Chen, B. Wysocki, and T. Huang. “The circuit realization of a neuromorphic computing system with memristor-based synapse design.” In Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 7663 LNCS:357–65, 2012. https://doi.org/10.1007/978-3-642-34475-6_43.

Bi, X., H. Li, and X. Wang. “STT-RAM cell design considering CMOS and MTJ temperature dependence.” IEEE Transactions on Magnetics 48, no. 11 (October 29, 2012): 3821–24. https://doi.org/10.1109/TMAG.2012.2200469.

Zhang, Y., W. Wen, and Y. Chen. “The prospect of STT-RAM scaling from readability perspective.” IEEE Transactions on Magnetics 48, no. 11 (October 29, 2012): 3035–38. https://doi.org/10.1109/TMAG.2012.2203589.

Bi, X., H. Li, and J. J. Kim. “Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design.” In Proceedings 2012 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2012, 374–79, 2012. https://doi.org/10.1109/ISVLSI.2012.56.

Shao, Z., Y. Liu, Y. Chen, and T. Li. “Utilizing PCM for energy optimization in embedded systems.” In Proceedings 2012 IEEE Computer Society Annual Symposium on VLSI Isvlsi 2012, 398–403, 2012. https://doi.org/10.1109/ISVLSI.2012.81.

Chen, Y. C., H. Li, and W. Zhang. “A novel peripheral circuit for RRAM-based LUT.” In Iscas 2012 2012 IEEE International Symposium on Circuits and Systems, 1811–14, 2012. https://doi.org/10.1109/ISCAS.2012.6271619.

Chen, Y. C., H. H. Li, W. Zhang, and R. E. Pino. “The 3-D stacking bipolar RRAM for high density.” IEEE Transactions on Nanotechnology 11, no. 5 (September 17, 2012): 948–56. https://doi.org/10.1109/TNANO.2012.2208759.

Li, Y., Y. Chen, and A. K. Jones. “A software approach for combating asymmetries of non-volatile memories.” In Proceedings of the International Symposium on Low Power Electronics and Design, 191–96, 2012. https://doi.org/10.1145/2333660.2333708.

Sun, Z., H. Li, and W. Wu. “A dual-mode architecture for fast-switching STT-RAM.” In Proceedings of the International Symposium on Low Power Electronics and Design, 45–50, 2012. https://doi.org/10.1145/2333660.2333673.

Sun, Z., X. Bi, and H. Li. “Process variation aware data management for STT-RAM cache design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 179–84, 2012. https://doi.org/10.1145/2333660.2333706.

Sun, G., Y. Zhang, Y. Wang, and Y. Chen. “Improving energy efficiency of write-asymmetric memories by log style write.” In Proceedings of the International Symposium on Low Power Electronics and Design, 173–78, 2012. https://doi.org/10.1145/2333660.2333705.

Zhang, Y., W. Wen, and Y. Chen. “STT-Ram cell design considering MTJ asymmetric switching.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400073.

Li, H. H., and Z. Sun. “Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement.” Spin 2, no. 3 (September 1, 2012). https://doi.org/10.1142/S2010324712400085.

Hu, M., H. Li, Q. Wu, G. S. Rose, and Y. Chen. “Memristor crossbar based hardware realization of BSB recall function.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252563.

Wang, H., H. Li, and R. E. Pino. “Memristor-based synapse design and training scheme for neuromorphic computing architecture.” In Proceedings of the International Joint Conference on Neural Networks, 2012. https://doi.org/10.1109/IJCNN.2012.6252577.

Hu, M., H. Li, Q. Wu, and G. S. Rose. “Hardware realization of BSB recall function using memristor crossbar arrays.” In Proceedings Design Automation Conference, 498–503, 2012. https://doi.org/10.1145/2228360.2228448.

Wen, W., Y. Zhang, Y. Chen, Y. Wang, and Y. Xie. “PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method.” In Proceedings Design Automation Conference, 1191–96, 2012. https://doi.org/10.1145/2228360.2228580.

Chen, X., J. Zheng, Y. Chen, M. Zhao, and C. J. Xue. “Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices.” In Proceedings Design Automation Conference, 1000–1005, 2012. https://doi.org/10.1145/2228360.2228540.

Pino, R. E., H. Li, Y. Chen, M. Hu, and B. Liu. “Statistical memristor modeling and case study in neuromorphic computing.” In Proceedings Design Automation Conference, 585–90, 2012. https://doi.org/10.1145/2228360.2228466.