Publications

Liu, C., and H. Li. “A weighted sensing scheme for ReRAM-based cross-point memory array.” In Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi, 65–70, 2014. https://doi.org/10.1109/ISVLSI.2014.32.

Hu, X., G. Feng, H. Li, Y. Chen, and S. Duan. “An adjustable memristor model and its application in small-world neural networks.” In Proceedings of the International Joint Conference on Neural Networks, 7–14, 2014. https://doi.org/10.1109/IJCNN.2014.6889605.

Chen, L., C. Li, T. Huang, X. He, H. Li, and Y. Chen. “STDP learning rule based on memristor with STDP property.” In Proceedings of the International Joint Conference on Neural Networks, 1–6, 2014. https://doi.org/10.1109/IJCNN.2014.6889506.

Zhang, Y., W. Wen, H. Li, and Y. Chen. “The Prospect of STT-RAM Scaling.” In Metallic Spintronic Devices. CRC Press, 2014.

Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.

Chen, L., C. Li, T. Huang, Y. Chen, and X. Wang. “Memristor crossbar-based unsupervised image learning.” Neural Computing and Applications 25, no. 2 (August 1, 2014): 393–400. https://doi.org/10.1007/s00521-013-1501-0.

Chen, Ying, Peng Liu, and Zhi Wu Yu. “Research on the Sol-Gel Method of Preparing Ternary Nano SiO₂-Al₂O₃-TiO₂ Materials.” In Key Engineering Materials, 609–610:281–87. Trans Tech Publications, Ltd., 2014. https://doi.org/10.4028/www.scientific.net/kem.609-610.281.

Li, B., Y. Wang, Y. Weng, Y. Chen, and H. Yang. “Training itself: Mixed-signal training acceleration for memristor-based neural network.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 361–66, 2014. https://doi.org/10.1109/ASPDAC.2014.6742916.

Hu, M., Y. Wang, Q. Qiu, Y. Chen, and H. Li. “The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 831–36, 2014. https://doi.org/10.1109/ASPDAC.2014.6742993.

Wang, J., Y. Tim, W. F. Wong, Z. L. Ong, Z. Sun, and H. H. Li. “A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 610–15, 2014. https://doi.org/10.1109/ASPDAC.2014.6742958.

Mao, M., G. Sun, Y. Li, A. K. Jones, and Y. Chen. “Prefetching techniques for STT-RAM based last-level cache in CMP systems.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 67–72, 2014. https://doi.org/10.1109/ASPDAC.2014.6742868.

Guo, J., Z. Chen, D. Wang, Z. Shao, and Y. Chen. “DPA: A data pattern aware error prevention technique for NAND flash lifetime extension.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 592–97, 2014. https://doi.org/10.1109/ASPDAC.2014.6742955.

Liu, X., Y. Li, Y. Zhang, A. K. Jones, and Y. Chen. “STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 355–60, 2014. https://doi.org/10.1109/ASPDAC.2014.6742915.

Liu, X., M. Mao, H. Li, Y. Chen, H. Jiang, J. J. Yang, Q. Wu, and M. Barnell. “A heterogeneous computing system with memristor-based neuromorphic accelerators.” In 2014 IEEE High Performance Extreme Computing Conference Hpec 2014, 2014. https://doi.org/10.1109/HPEC.2014.7040986.

Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” IEEE Transactions on Very Large Scale Integration VLSI Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.

Li, X., S. Duan, L. Wang, T. Huang, and Y. Chen. “Memristive radial basis function neural network for parameters adjustment of PID controller.” In Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 8866:150–58, 2014. https://doi.org/10.1007/978-3-319-12436-0_17.

Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies Design Architecture and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.

Wang, D., J. Guo, K. Bu, and Y. Chen. “Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.” In 2014 International Conference on Computing Networking and Communications Icnc 2014, 259–63, 2014. https://doi.org/10.1109/ICCNC.2014.6785342.

Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 126–31. IEEE, 2014.

Wen, W., Y. Zhang, M. Mao, and Y. Chen. “STT-RAM reliability enhancement through ECC and access scheme optimization.” In Proceedings of the International Symposium on Consumer Electronics ISCE, 2014. https://doi.org/10.1109/ISCE.2014.6884324.

Li, B., Y. Wang, Y. Chen, H. H. Li, and H. Yang. “ICE: Inline calibration for memristor crossbar-based computing engine.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.197.

Chen, L., C. Li, T. Huang, H. G. Ahmad, and Y. Chen. “A phenomenological memristor model for short-term/long-term memory.” Physics Letters Section A General Atomic and Solid State Physics 378, no. 40 (January 1, 2014): 2924–30. https://doi.org/10.1016/j.physleta.2014.08.018.

Nixon, K. W., X. Chen, H. Zhou, Y. Liu, and Y. Chen. “Mobile GPU power consumption reduction via dynamic resolution and frame rate scaling.” In 6th Workshop on Power Aware Computing and Systems Hotpower 2014, 2014.

Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” TheScientificWorldJournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.

Bu, K., Y. R. Chen, H. Xu, W. Yi, and Q. Y. Xie. “NAND flash service lifetime estimate with recovery effect and retention time relaxation.” Journal of Central South University 21, no. 8 (January 1, 2014): 3205–13. https://doi.org/10.1007/s11771-014-2292-x.