Publications

Hassan, A. M., C. Yang, C. Liu, H. Li, and Y. Chen. “Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.” In Proceedings of the 2017 Design Automation and Test in Europe Date 2017, 776–81, 2017. https://doi.org/10.23919/DATE.2017.7927094.

Cheng, H. P., W. Wen, C. Wu, S. Li, H. Li, and Y. Chen. “Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.” In Proceedings of the 2017 Design Automation and Test in Europe Date 2017, 139–44, 2017. https://doi.org/10.23919/DATE.2017.7926972.

Chen, L., J. Li, Y. Chen, Q. Deng, J. Shen, X. Liang, and L. Jiang. “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.” In Proceedings of the 2017 Design Automation and Test in Europe Date 2017, 19–24, 2017. https://doi.org/10.23919/DATE.2017.7926952.

Song, L., X. Qian, H. Li, and Y. Chen. “PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.” In Proceedings International Symposium on High Performance Computer Architecture, 541–52, 2017. https://doi.org/10.1109/HPCA.2017.55.

Cline, B. T., S. Heinrich-Barna, P. J. Wright, H. Li, V. Viswanath, S. Hu, P. Wesling, G. Qu, S. Ghosh, and A. A. Iranmanesh. “Welcome.” In Proceedings International Symposium on Quality Electronic Design Isqed, 2017. https://doi.org/10.1109/ISQED.2017.7918277.

Chai, X., Z. Gan, Y. Lu, Y. Chen, and D. Han. “A novel image encryption algorithm based on the chaotic system and DNA computing.” International Journal of Modern Physics C 28, no. 5 (May 1, 2017). https://doi.org/10.1142/S0129183117500693.

Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” IEEE Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.

Pan, C., M. Xie, C. Yang, Y. Chen, and J. Hu. “Exploiting multiple write modes of Nonvolatile main memory in embedded systems.” ACM Transactions on Embedded Computing Systems 16, no. 4 (May 1, 2017). https://doi.org/10.1145/3063130.

Chen, X., N. Khoshavi, R. F. Demara, J. Wang, D. Huang, W. Wen, and Y. Chen. “Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache.” IEEE Transactions on Computers 66, no. 5 (May 1, 2017): 786–98. https://doi.org/10.1109/TC.2016.2625245.

Chai, X., Z. Gan, Y. Chen, and Y. Zhang. “A visually secure image encryption scheme based on compressive sensing.” Signal Processing 134 (May 1, 2017): 35–51. https://doi.org/10.1016/j.sigpro.2016.11.016.

Chai, Xiuli, Zhihua Gan, Yang Lu, Yiran Chen, and Daojun Han. “A novel image encryption algorithm based on the chaotic system and DNA computing.” International Journal of Modern Physics C 28, no. 05 (May 2017): 1–24.

Bayram, I., E. Eken, D. Kline, N. Parshook, Y. Chen, and A. K. Jones. “Modeling STT-RAM fabrication cost and impacts in NVSim.” In 2016 7th International Green and Sustainable Computing Conference Igsc 2016, 2017. https://doi.org/10.1109/IGCC.2016.7892599.

Guo, J., D. Wang, Z. Shao, and Y. Chen. “Data-Pattern-Aware Error Prevention Technique to Improve System Reliability.” IEEE Transactions on Very Large Scale Integration VLSI Systems 25, no. 4 (April 1, 2017): 1433–43. https://doi.org/10.1109/TVLSI.2016.2642055.

Chai, X., Z. Gan, K. Yang, Y. Chen, and X. Liu. “An image encryption algorithm based on the memristive hyperchaotic system, cellular automata and DNA sequence operations.” Signal Processing Image Communication 52 (March 1, 2017): 6–19. https://doi.org/10.1016/j.image.2016.12.007.

Wang, Y., W. Wen, L. Song, and H. Li. “Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 776–81, 2017. https://doi.org/10.1109/ASPDAC.2017.7858418.

Yin, S., D. Kadetotad, B. Yan, C. Song, Y. Chen, C. Chakrabarti, and J. S. Seo. “Low-power neuromorphic speech recognition engine with coarse-grain sparsity.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 111–14, 2017. https://doi.org/10.1109/ASPDAC.2017.7858305.

Min, C., J. Guo, H. Li, and Y. Chen. “Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 764–69, 2017. https://doi.org/10.1109/ASPDAC.2017.7858416.

Liu, C., Q. Yang, C. Zhang, H. Jiang, Q. Wu, and H. Li. “A memristor-based neuromorphic engine with a current sensing scheme for artificial neural network applications.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 647–52, 2017. https://doi.org/10.1109/ASPDAC.2017.7858397.

Chai, X. L., Z. H. Gan, K. Yuan, Y. Lu, and Y. R. Chen. “An image encryption scheme based on three-dimensional Brownian motion and chaotic system.” Chinese Physics B 26, no. 2 (February 1, 2017). https://doi.org/10.1088/1674-1056/26/2/020504.

Zhang, P., C. Li, T. Huang, L. Chen, and Y. Chen. “Forgetting memristor based neuromorphic system for pattern training and recognition.” Neurocomputing 222 (January 26, 2017): 47–53. https://doi.org/10.1016/j.neucom.2016.10.012.

Li, H. H., P. Ghosal, and T. Theocharides. “Message from the Technical Program Chairs.” In Proceedings 2016 IEEE International Symposium on Nanoelectronic and Information Systems Inis 2016, xiii–xiv, 2017. https://doi.org/10.1109/iNIS.2016.007.

Li, H., and Y. Chen. Nonvolatile memory design: Magnetic, resistive, and phase change, 2017. https://doi.org/10.1201/b11354.

Park, J., H. Li, S. Li, W. Wen, Y. Chen, P. T. P. Tang, and P. Dubey. “Faster cnns with direct sparse convolutions and guided pruning.” In 5th International Conference on Learning Representations Iclr 2017 Conference Track Proceedings, 2017.

Li, H. H., Y. Chen, C. Liu, J. P. Strachan, and N. Davila. “Looking Ahead for Resistive Memory Technology: A broad perspective on ReRAM technology for future storage and computing.” IEEE Consumer Electronics Magazine 6, no. 1 (January 1, 2017): 94–103. https://doi.org/10.1109/MCE.2016.2614523.

Chen, Y. C., Y. Wang, W. Zhang, Y. Chen, and H. H. Li. “In-place logic obfuscation for emerging nonvolatile FPGAs.” In Fundamentals of Ip and Soc Security Design Verification and Debug, 277–93, 2017. https://doi.org/10.1007/978-3-319-50057-7_11.