Publications

Bi, X., Z. Sun, H. Li, and W. Wu. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 88–94, 2012. https://doi.org/10.1145/2429384.2429401.

Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity.” Neural Plasticity 2012 (January 2012): 272374. https://doi.org/10.1155/2012/272374.

Sun, Z., X. Bi, H. Li, W. F. Wong, Z. L. Ong, X. Zhu, and W. Wu. “Multi retention level STT-RAM cache designs with a dynamic refresh scheme.” In Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 329–38, 2011. https://doi.org/10.1145/2155620.2155659.

Hu, M., H. Li, and R. E. Pino. “Fast statistical model of TiO 2 thin-film memristor and design implication.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 345–52, 2011. https://doi.org/10.1109/ICCAD.2011.6105353.

Zhou, P., B. Zhao, Y. Zhang, J. Yang, and Y. Chen. “MRAC: A memristor-based reconfigurable framework for adaptive cache replacement.” In Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 207–8, 2011. https://doi.org/10.1109/PACT.2011.29.

Joshi, R., R. Kanj, P. Wang, and H. H. Li. “Universal statistical cure for predicting memory loss.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 236–39, 2011. https://doi.org/10.1109/ICCAD.2011.6105333.

Zhang, Y., X. Wang, and Y. Chen. “STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 471–77, 2011. https://doi.org/10.1109/ICCAD.2011.6105370.

Xue, C. J., Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li. “Emerging non-volatile memories: Opportunities and challenges.” In Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS’11, 325–34, 2011. https://doi.org/10.1145/2039370.2039420.

Wang, P., X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu. “A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.” In Proceedings of the Custom Integrated Circuits Conference, 2011. https://doi.org/10.1109/CICC.2011.6055392.

Chen, Y., W. F. Wong, H. Li, and C. K. Koh. “Processor caches built using multi-level spin-transfer torque RAM cells.” In Proceedings of the International Symposium on Low Power Electronics and Design, 73–78, 2011. https://doi.org/10.1109/ISLPED.2011.5993610.

Chen, Y. C., H. Li, W. Zhang, and R. E. Pino. “3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design.” In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, 59–64, 2011. https://doi.org/10.1109/NANOARCH.2011.5941484.

Chen, Y. C., H. Li, Y. Chen, and R. E. Pino. “3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers.” In Proceedings -Design, Automation and Test in Europe, DATE, 583–86, 2011.

Dong, X., X. Wu, Y. Xie, Y. Chen, and H. Li. “Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation.” IET Computers and Digital Techniques 5, no. 3 (May 1, 2011): 213–20. https://doi.org/10.1049/iet-cdt.2009.0091.

Hu, M., H. Li, Y. Chen, X. Wang, and R. E. Pino. “Geometry variations analysis of TiO2 thin-film and spintronic memristors.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25–30, 2011. https://doi.org/10.1109/ASPDAC.2011.5722193.

Chen, Y., and H. Li. “Emerging sensing techniques for emerging memories.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 204–10, 2011. https://doi.org/10.1109/ASPDAC.2011.5722185.

Xu, W., H. Sun, X. Wang, Y. Chen, and T. Zhang. “Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM).” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 3 (March 1, 2011): 483–93. https://doi.org/10.1109/TVLSI.2009.2035509.

Hu, M., H. H. Li, Y. Chen, and X. Wang. “Spintronic memristor: Compact model and statistical analysis.” Journal of Low Power Electronics 7, no. 2 (January 1, 2011): 234–44. https://doi.org/10.1166/jolpe.2011.1131.

Wang, P., X. Wang, Y. Zhang, H. Li, S. P. Levitan, and Y. Chen. “Nonpersistent errors optimization in spin-MOS logic and storage circuitry.” IEEE Transactions on Magnetics 47, no. 10 (January 1, 2011): 3860–63. https://doi.org/10.1109/TMAG.2011.2153838.

Zhang, Y., X. Wang, H. Li, and Y. Chen. “STT-RAM cell optimization considering MTJ and CMOS variations.” IEEE Transactions on Magnetics 47, no. 10 (January 1, 2011): 2962–65. https://doi.org/10.1109/TMAG.2011.2158810.

Li, H., X. Wang, Z. L. Ong, W. F. Wong, Y. Zhang, P. Wang, and Y. Chen. “Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement.” IEEE Transactions on Magnetics 47, no. 10 (January 1, 2011): 2356–59. https://doi.org/10.1109/TMAG.2011.2159262.

Joshi, Rajiv, Rouwaida Kanj, Peiyuan Wang, and Hai Helen Li. “Universal Statistical Cure For Predicting Memory Loss (Invited Paper).” In 2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 236–39. IEEE, 2011.

Zhang, Y., W. Wen, and Y. Chen. “Asymmetry in STT-RAM cell operations.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:117–44, 2011. https://doi.org/10.1007/978-1-4419-9551-3_5.

Zhu, W., H. Li, Y. Chen, and X. Wang. “Current switching in MgO-based magnetic tunneling junctions.” IEEE Transactions on Magnetics 47, no. 1 PART 2 (January 1, 2011): 156–60. https://doi.org/10.1109/TMAG.2010.2085441.

Chen, Y., H. Li, X. Wang, and J. Park. “Applications of TMR devices in solid state circuits and systems.” In 2010 International SoC Design Conference, ISOCC 2010, 252–55, 2010. https://doi.org/10.1109/SOCDC.2010.5682923.

Chen, Y., X. Wang, H. Li, H. Xi, Y. Yan, and W. Zhu. “Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 12 (December 1, 2010): 1724–34. https://doi.org/10.1109/TVLSI.2009.2032192.