Cross-Layer Design Techniques for Robustness of the Next-Generation Nonvolatile Memories
The objective of the research is to develop design technologies that can alleviate the general robustness issues of the next-generation nonvolatile memories while maintaining and even improving the generic memory specifications such as density, power and performance. Comprehensive solutions are integrated from architecture, circuit and device layers for the improvement on the density, cost and reliability of emerging nonvolatile memories.
SMURFS: Statistical Modeling, SimUlation and Robust Design Techniques For MemriStors
The fourth fundamental passive circuit element − memristor, has demonstrated great potentials in massive data storage, neuromorphic computing, signal processing, biomedical lab-on-a-chip, sensing etc. The objective of this research is to investigate the design implications of process variations and environmental fluctuations to memristor-based VLSI systems, to exploit a fast statistical simulation technique, and to explore new circuit techniques to improve the memristive system reliability and robustness.
STEMS: STatistic Emerging Memory Simulator
Emerging memory technologies such as Magnetoresistive random-access memory (MRAM), Phase-change memory (PCRAM), and Resistive random-access memory (RRAM) are being explored as potential alternatives for future computing systems. However, traditional memory design methodologies are not sufficient to address probabilistic behaviors, which are caused by process variations and the intrinsic randomness in the physical mechanisms (e.g., thermal fluctuations) of these emerging technologies. The objective of this research is to develop a design methodology called STatistical Emerging Memory Simulator (STEMS) for circuit/architecture designs with such emerging memory technologies.
Nonvolatile TCAM Circuit Design Based on Spintronic Technology
As process technology scales down rapidly, conventional SRAM based ternary content-addressable memories (TCAMs) design becomes even more challenging for its aggressive requirements in high storage density, fast access speed, and low pow r consumption. This project explores the nonvolatile TCAM circuit and architecture based on spintronic technology.
Novel Capacitor-less DRAM Technology with Energy Efficiency, Manufacturability, and Scalability
DRAM – an essential memory component of PCs, mobile devices, and other electronics – has no known substitutes to date. This project focuses on commercializing a manufacturable, scalable, and ultra-low power replacement called Ferroelectric DRAM (FEDRAM). Due to its novel architecture, FEDRAM will unblock many of the obstacles that are currently hindering the DRAM industry (i.e. density scaling in accordance with Moore’s Law). While it remains difficult for many emerging memory technologies to gain traction, FEDRAM can be manufactured using existing facilities and equipment; therefore, it benefits from a relatively short time-to-market, and is cost-competitive with existing DRAM.
Spintronic Memory and Logic
Recently, the giant spin-hall effect (GSHE) as a phenomenon that occurs in metals with large atomic weights has raised significant attention in magnetic memory and logic development. More specific, in metals with large atomic weights, electrons with different spins are deflected in different sideways directions. Consequently, applying a charge current can generate a flow of spin angular momentum transverse to the charge flow. The objective of this project includes developing the GSHE device model based on the measurement data provided by Qualcomm Inc. and investigating the new memory and logic design by leveraging the new device.