Publications

Found 336 results
Type [ Year(Asc)]
2018
X Chai, X Zheng, Z Gan, D Han, and Y Chen. "An image encryption algorithm based on chaotic system and compressive sensing." Signal Processing 148 (2018): 124-144.
I Bayram, and Y Chen. "NV-TCAM: Alternative designs with NVM devices." Integration, the VLSI Journal (2018).
2017
L Chen, J Li, Y Chen, Q Deng, J Shen, X Liang, and L Jiang. "Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar." In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 19-24. 2017.
J Mao, Z Qin, Z Xu, KW Nixon, X Chen, H Li, and Y Chen. "AdaLearner: An adaptive distributed mobile learning system for neural networks." In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 291-296. Vol. 2017-November. 2017.
Y Wang, W Wen, L Song, and H Li. "Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses." In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 776-781. 2017.
B Yan, J Yang, Q Wu, Y Chen, and H Li. "A closed-loop design to enhance weight stability of memristor based neural network chips." In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, 541-548. Vol. 2017-November. 2017.
M Hu, Y Chen, JJ Yang, Y Wang, and HH Li. "A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 8 (2017): 1353-1366.
H Li, and. "Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies." 2017.
X Bi, M Mao, D Wang, and HH Li. "Cross-Layer Optimization for Multilevel Cell STT-RAM Caches." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 6 (2017): 1807-1820.
J Guo, D Wang, Z Shao, and Y Chen. "Data-Pattern-Aware Error Prevention Technique to Improve System Reliability." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 4 (2017): 1433-1443.
X Chen, N Khoshavi, RF DeMara, J Wang, D Huang, W Wen, and Y Chen. "Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache." IEEE Transactions on Computers 66, no. 5 (2017): 786-798.
M Mao, W Wen, Y Zhang, Y Chen, and H Li. "An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory." IEEE Transactions on Computers 66, no. 9 (2017): 1478-1490.
C Pan, M Xie, C Yang, Y Chen, and J Hu. "Exploiting Multiple Write Modes of Nonvolatile Main Memory in Embedded Systems." ACM Transactions on Embedded Computing Systems 16, no. 4 (2017): 1-26.
C Min, J Guo, H Li, and Y Chen. "Extending the lifetime of object-based NAND flash device with STT-RAM/DRAM hybrid buffer." In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 764-769. 2017.
J Guo, W Wen, J Hu, D Wang, H Li, and Y Chen. "FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 7 (2017): 1167-1180.
P Zhang, C Li, T Huang, L Chen, and Y Chen. "Forgetting memristor based neuromorphic system for pattern training and recognition." Neurocomputing 222 (2017): 47-53.
S Li, W Wen, Y Wang, S Han, Y Chen, and HH Li. "An FPGA design framework for CNN sparsification and acceleration." In Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017. 2017.
E Eken, I Bayram, Y Zhang, B Yan, W Wu, HH Li, and Y Chen. "Giant Spin-Hall assisted STT-RAM and logic design." Integration, the VLSI Journal 58 (2017): 253-261.
Y Wang, W Wen, B Liu, D Chiarulli, and HH Li. "Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks." In Design Automation Conference. Vol. Part 128280. 2017.
SP MOHANTY, X Li, H Li, and Y CAO. "Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing." IEEE Transactions on Nanotechnology 16, no. 3 (2017): 383-386.
Y Chen, T-W Kuo, and B de Salvo. "Guest Editors’ Introduction: Critical and Enabling Techniques for Emerging Memories." IEEE Design and Test 34, no. 3 (2017): 6-7.
AM Hassan, HH Li, and Y Chen. "Hardware implementation of echo state networks using memristor double crossbar arrays." In Proceedings of the International Joint Conference on Neural Networks, 2171-2177. Vol. 2017-May. 2017.
AM Hassan, C Yang, C Liu, H Li, and Y Chen. "Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays." In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 776-781. 2017.
X Chai, Z Gan, K Yang, Y Chen, and X Liu. "An image encryption algorithm based on the memristive hyperchaotic system, cellular automata and DNA sequence operations." Signal Processing: Image Communication 52 (2017): 6-19.
X-L Chai, Z-H Gan, K Yuan, Y Lu, and Y-R Chen. "An image encryption scheme based on three-dimensional Brownian motion and chaotic system." Chinese Physics B 26, no. 2 (2017): 020504.

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