Publications

Li, H., M. Hu, and R. Pino. “Statistical Memristor Model and Its Applications in Neuromorphic Computing.” In Advances in Neuromorphic Memristor Science and Applications, edited by R. Kozma, R. Pino, and G. Pazienza. Springer Science & Business Media, 2012.

Sun, Z., X. Chen, Y. Zhang, H. Li, and Y. Chen. “Nonvolatile memories as the data storage system for implantable ecg recorder.” ACM Journal on Emerging Technologies in Computing Systems 8, no. 2 (June 1, 2012). https://doi.org/10.1145/2180878.2180885.

Bi, X., C. Zhang, H. Li, Y. Chen, and R. E. Pino. “Spintronic memristor based temperature sensor design with CMOS current reference.” In Proceedings Design Automation and Test in Europe Date, 1301–6, 2012.

Zhang, Y., X. Wang, Y. Li, A. K. Jones, and Y. Chen. “Asymmetry of MTJ switching and its implication to STT-RAM designs.” In Proceedings Design Automation and Test in Europe Date, 1313–18, 2012.

Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Architecting a common-source-line array for bipolar non-volatile memory devices.” In Proceedings Design Automation and Test in Europe Date, 1451–54, 2012.

Chen, Y., Y. Zhang, and P. Wang. “Probabilistic design in spintronic memory and logic circuit.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 323–28, 2012. https://doi.org/10.1109/ASPDAC.2012.6164967.

Chen, X., J. Zeng, Y. Chen, W. Zhang, and H. Li. “Fine-grained dynamic voltage scaling on OLED display.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 807–12, 2012. https://doi.org/10.1109/ASPDAC.2012.6165066.

Chen, Y. C., W. Zhang, and H. Li. “A look up table design with 3D bipolar RRAMs.” In Proceedings of the Asia and South Pacific Design Automation Conference ASP DAC, 73–78, 2012. https://doi.org/10.1109/ASPDAC.2012.6165051.

Sun, Z., H. Li, and X. Wang. “Magnetic tunnel junction design margin exploration for self-reference sensing scheme.” Journal of Applied Physics 111, no. 7 (April 2012): 7C726–7263. https://doi.org/10.1063/1.3679647.

Chen, Y., H. Li, X. Wang, W. Zhu, W. Xu, and T. Zhang. “A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme.” IEEE Journal of Solid State Circuits 47, no. 2 (February 1, 2012): 560–73. https://doi.org/10.1109/JSSC.2011.2170778.

Sun, Z., H. Li, Y. Chen, and X. Wang. “Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory.” IEEE Transactions on Very Large Scale Integration VLSI Systems 20, no. 11 (January 1, 2012): 2020–30. https://doi.org/10.1109/TVLSI.2011.2166282.

Bi, X., Z. Sun, H. Li, and W. Wu. “Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 88–94, 2012. https://doi.org/10.1145/2429384.2429401.

Wang, Hui, Andrea Megill, Kaiwen He, Alfredo Kirkwood, and Hey-Kyoung Lee. “Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity.” Neural Plasticity 2012 (January 2012): 272374. https://doi.org/10.1155/2012/272374.

Chen, Y., H. Li, Y. Xie, and D. Niu. “Low Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing. CRC Press, 2012.

Wang, P., W. Zhang, R. Joshi, R. Kanj, and Y. Chen. “A thermal and process variation aware MTJ switching model and its applications in soft error analysis.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 720–27, 2012. https://doi.org/10.1145/2429384.2429541.

Chen, X., B. Liu, Y. Chen, M. Zhao, C. J. Xue, and X. Guo. “Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 516–22, 2012. https://doi.org/10.1145/2429384.2429493.

Zhou, P., B. Zhao, Y. Zhang, J. Yang, and Y. Chen. “MRAC: A memristor-based reconfigurable framework for adaptive cache replacement.” In Parallel Architectures and Compilation Techniques Conference Proceedings Pact, 207–8, 2011. https://doi.org/10.1109/PACT.2011.29.

Joshi, R., R. Kanj, P. Wang, and H. H. Li. “Universal statistical cure for predicting memory loss.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 236–39, 2011. https://doi.org/10.1109/ICCAD.2011.6105333.

Zhang, Y., X. Wang, and Y. Chen. “STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 471–77, 2011. https://doi.org/10.1109/ICCAD.2011.6105370.

Sun, Z., X. Bi, H. Li, W. F. Wong, Z. L. Ong, X. Zhu, and W. Wu. “Multi retention level STT-RAM cache designs with a dynamic refresh scheme.” In Proceedings of the Annual International Symposium on Microarchitecture Micro, 329–38, 2011. https://doi.org/10.1145/2155620.2155659.

Hu, M., H. Li, and R. E. Pino. “Fast statistical model of TiO 2 thin-film memristor and design implication.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 345–52, 2011. https://doi.org/10.1109/ICCAD.2011.6105353.

Xue, C. J., Y. Zhang, Y. Chen, G. Sun, J. J. Yang, and H. Li. “Emerging non-volatile memories: Opportunities and challenges.” In Embedded Systems Week 2011 Esweek 2011 Proceedings of the 9th IEEE ACM IFIP International Conference on Hardware Software Codesign and System Synthesis Codes Isss 11, 325–34, 2011. https://doi.org/10.1145/2039370.2039420.

Wang, P., X. Chen, Y. Chen, H. Li, S. Kang, X. Zhu, and W. Wu. “A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.” In Proceedings of the Custom Integrated Circuits Conference, 2011. https://doi.org/10.1109/CICC.2011.6055392.

Chen, Y., W. F. Wong, H. Li, and C. K. Koh. “Processor caches built using multi-level spin-transfer torque RAM cells.” In Proceedings of the International Symposium on Low Power Electronics and Design, 73–78, 2011. https://doi.org/10.1109/ISLPED.2011.5993610.

Chen, Y. C., H. Li, W. Zhang, and R. E. Pino. “3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design.” In Proceedings of the 2011 IEEE ACM International Symposium on Nanoscale Architectures Nanoarch 2011, 59–64, 2011. https://doi.org/10.1109/NANOARCH.2011.5941484.