Publications

Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 126–31. IEEE, 2014.

Wen, W., Y. Zhang, M. Mao, and Y. Chen. “STT-RAM reliability enhancement through ECC and access scheme optimization.” In Proceedings of the International Symposium on Consumer Electronics ISCE, 2014. https://doi.org/10.1109/ISCE.2014.6884324.

Li, B., Y. Wang, Y. Chen, H. H. Li, and H. Yang. “ICE: Inline calibration for memristor crossbar-based computing engine.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.197.

Chen, L., C. Li, T. Huang, H. G. Ahmad, and Y. Chen. “A phenomenological memristor model for short-term/long-term memory.” Physics Letters Section A General Atomic and Solid State Physics 378, no. 40 (January 1, 2014): 2924–30. https://doi.org/10.1016/j.physleta.2014.08.018.

Nixon, K. W., X. Chen, H. Zhou, Y. Liu, and Y. Chen. “Mobile GPU power consumption reduction via dynamic resolution and frame rate scaling.” In 6th Workshop on Power Aware Computing and Systems Hotpower 2014, 2014.

Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” TheScientificWorldJournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.

Bu, K., Y. R. Chen, H. Xu, W. Yi, and Q. Y. Xie. “NAND flash service lifetime estimate with recovery effect and retention time relaxation.” Journal of Central South University 21, no. 8 (January 1, 2014): 3205–13. https://doi.org/10.1007/s11771-014-2292-x.

Park, E., S. Yoo, S. Lee, and H. Li. “Accelerating graph computation with racetrack memory and pointer-assisted graph representation.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.172.

Zhang, C., G. Sun, P. Li, T. Wang, D. Niu, and Y. Chen. “SBAC: A statistics based cache bypassing method for asymmetric-access caches.” In Proceedings of the International Symposium on Low Power Electronics and Design, 345–50, 2014. https://doi.org/10.1145/2627369.2627611.

Chen, L., C. Li, T. Huang, Y. Chen, S. Wen, and J. Qi. “A synapse memristor model with forgetting effect.” Physics Letters Section A General Atomic and Solid State Physics 377, no. 45–48 (December 17, 2013): 3260–65. https://doi.org/10.1016/j.physleta.2013.10.024.

Wang, J., Y. Tim, W. F. Wong, and H. H. Li. “A practical low-power memristor-based analog neural branch predictor.” In Proceedings of the International Symposium on Low Power Electronics and Design, 175–80, 2013. https://doi.org/10.1109/ISLPED.2013.6629290.

Li, B., Y. Shan, M. Hu, Y. Wang, Y. Chen, and H. Yang. “Memristor-based approximated computation.” In Proceedings of the International Symposium on Low Power Electronics and Design, 242–47, 2013. https://doi.org/10.1109/ISLPED.2013.6629302.

Chen, Q., Q. Qiu, H. Li, and Q. Wu. “A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 202–5, 2013. https://doi.org/10.1109/ICCAD.2013.6691119.

Zhang, Y., I. Bayram, Y. Wang, H. Li, and Y. Chen. “ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 9–16, 2013. https://doi.org/10.1109/ICCAD.2013.6691091.

Jones, A. K., Y. Chen, W. O. Collinge, H. Xu, L. A. Schaefer, A. E. Landis, and M. M. Bilec. “Considering fabrication in sustainable computing.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 206–10, 2013. https://doi.org/10.1109/ICCAD.2013.6691120.

Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.

Wen, W., M. Mao, X. Zhu, S. H. Kang, D. Wang, and Y. Chen. “CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 1–8, 2013. https://doi.org/10.1109/ICCAD.2013.6691090.

Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.

Li, J., L. Shi, Q. Li, C. J. Xue, Y. Chen, Y. Xu, and W. Wang. “Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.” ACM Transactions on Design Automation of Electronic Systems 19, no. 1 (December 1, 2013). https://doi.org/10.1145/2534393.

Ji, F., H. H. Li, B. Wysocki, C. Thiem, and N. McDonald. “Memristor-based synapse design and a case study in reconfigurable systems.” In Proceedings of the International Joint Conference on Neural Networks, 2013. https://doi.org/10.1109/IJCNN.2013.6706776.

Wen, Shiping, Gang Bao, Zhigang Zeng, Yiran Chen, and Tingwen Huang. “Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays.” Neural Networks : The Official Journal of the International Neural Network Society 48 (December 2013): 195–203. https://doi.org/10.1016/j.neunet.2013.10.001.

Chen, Z., L. Zhang, X. Bi, and H. Li. “A pseudo-weighted sensing scheme for memristor based cross-point memory.” In Proceedings of the 2013 IEEE ACM International Symposium on Nanoscale Architectures Nanoarch 2013, 38–39, 2013. https://doi.org/10.1109/NanoArch.2013.6623039.

Wen, S., Z. Zeng, T. Huang, and Y. Chen. “Fuzzy modeling and synchronization of different memristor-based chaotic circuits.” Physics Letters Section A General Atomic and Solid State Physics 377, no. 34–36 (November 1, 2013): 2016–21. https://doi.org/10.1016/j.physleta.2013.05.046.

Li, Hong-jun, Zheng-guang Xie, and Wei Hu. “An image compression method using sparse representation and grey relation.” In Proceedings of 2013 IEEE International Conference on Grey Systems and Intelligent Services (GSIS), 53–56. IEEE, 2013. https://doi.org/10.1109/gsis.2013.6714741.

Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” ACM Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.