Publications

Wu, C., B. Ni, and H. Li. “Redistributing and Re-Stylizing Features for Training a Fast Photorealistic Stylizer.” In Proceedings of the International Joint Conference on Neural Networks, 2020. https://doi.org/10.1109/IJCNN48605.2020.9207095.

Dai, P., J. Yang, X. Ye, X. Cheng, J. Luo, L. Song, Y. Chen, and W. Zhao. “SparseTrain: Exploiting dataflow sparsity for efficient convolutional neural networks training.” In Proceedings - Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218710.

Zheng, Q., Z. Wang, Z. Feng, B. Yan, Y. Cai, R. Huang, Y. Chen, C. L. Yang, and H. H. Li. “Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks.” In Proceedings - Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218590.

Li, Z., B. Yan, and H. H. Li. “ReSiPE: ReRAM-based single-spiking processing-in-memory engine.” In Proceedings - Design Automation Conference, Vol. 2020-July, 2020. https://doi.org/10.1109/DAC18072.2020.9218578.

Song, C., H. P. Cheng, H. Yang, S. Li, C. Wu, Q. Wu, and H. Li. “Adversarial Attack: A New Threat to Smart Devices and How to Defend It.” IEEE Consumer Electronics Magazine 9, no. 4 (July 1, 2020): 49–55. https://doi.org/10.1109/MCE.2020.2969150.

Kim, B., and H. Li. “Leveraging 3D vertical RRAM to developing neuromorphic architecture for pattern classification.” In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 2020-July:258–63, 2020. https://doi.org/10.1109/ISVLSI49217.2020.00054.

Chai, X., H. Wu, Z. Gan, Y. Zhang, and Y. Chen. “Hiding cipher-images generated by 2-D compressive sensing with a multi-embedding strategy.” Signal Processing 171 (June 1, 2020). https://doi.org/10.1016/j.sigpro.2020.107525.

Chai, X., X. Zheng, Z. Gan, and Y. Chen. “Exploiting plaintext-related mechanism for secure color image encryption.” Neural Computing and Applications 32, no. 12 (June 1, 2020): 8065–88. https://doi.org/10.1007/s00521-019-04312-8.

Yang, H., M. Tang, W. Wen, F. Yan, D. Hu, A. Li, H. Li, and Y. Chen. “Learning low-rank deep neural networks via singular vector orthogonality regularization and singular value sparsification.” In IEEE Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 2020-June:2899–2908, 2020. https://doi.org/10.1109/CVPRW50498.2020.00347.

Challapalle, N., S. Rampalli, L. Song, N. Chandramoorthy, K. Swaminathan, J. Sampson, Y. Chen, and V. Narayanan. “GaaS-X: Graph Analytics Accelerator Supporting Sparse Data Representation using Crossbar Architectures.” In Proceedings - International Symposium on Computer Architecture, 2020-May:433–45, 2020. https://doi.org/10.1109/ISCA45697.2020.00044.

Chai, X., X. Fu, Z. Gan, Y. Zhang, Y. Lu, and Y. Chen. “An efficient chaos-based image compression and encryption scheme using block compressive sensing and elementary cellular automata.” Neural Computing and Applications 32, no. 9 (May 1, 2020): 4961–88. https://doi.org/10.1007/s00521-018-3913-3.

Zhang, J., J. Huang, M. Deisher, H. Li, and Y. Chen. “Structural sparsification for far-field speaker recognition with intel R GNA.” In ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings, 2020-May:3037–41, 2020. https://doi.org/10.1109/ICASSP40776.2020.9054569.

Wang, S., Y. Cao, T. Huang, Y. Chen, and S. Wen. “Event-triggered distributed control for synchronization of multiple memristive neural networks under cyber-physical attacks.” Information Sciences 518 (May 1, 2020): 361–75. https://doi.org/10.1016/j.ins.2020.01.022.

Jia, X., J. Yang, P. Dai, R. Liu, Y. Chen, and W. Zhao. “SPINBIS: Spintronics-based Bayesian inference system with stochastic computing.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 4 (April 1, 2020): 789–802. https://doi.org/10.1109/TCAD.2019.2897631.

Inkawhich, N., E. Davis, U. Majumder, C. Capraro, and Y. Chen. “Advanced techniques for robust SAR ATR: Mitigating noise and phase errors.” In 2020 IEEE International Radar Conference, RADAR 2020, 844–49, 2020. https://doi.org/10.1109/RADAR42522.2020.9114784.

Zhang, G., B. Li, J. Wu, R. Wang, Y. Lan, L. Sun, S. Lei, H. Li, and Y. Chen. “A low-cost and high-speed hardware implementation of spiking neural network.” Neurocomputing 382 (March 21, 2020): 106–15. https://doi.org/10.1016/j.neucom.2019.11.045.

Sun, B., S. Wen, S. Wang, T. Huang, Y. Chen, and P. Li. “Quantized synchronization of memristive neural networks with time-varying delays via super-twisting algorithm.” Neurocomputing 380 (March 7, 2020): 133–40. https://doi.org/10.1016/j.neucom.2019.11.003.

Wang, Y., F. Chen, L. Song, C. J. Richard Shi, H. H. Li, and Y. Chen. “ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 1472–77, 2020. https://doi.org/10.23919/DATE48585.2020.9116422.

Joardar, B. K., N. Kannappan Jayakodi, J. R. Doppa, H. Li, P. P. Pande, and K. Chakrabarty. “GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 228–33, 2020. https://doi.org/10.23919/DATE48585.2020.9116273.

Zhang, S., B. Li, H. H. Li, and U. Schlichtmann. “A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines.” In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 1426–31, 2020. https://doi.org/10.23919/DATE48585.2020.9116323.

Chen, Y., Y. Xie, L. Song, F. Chen, and T. Tang. “A Survey of Accelerator Architectures for Deep Neural Networks.” Engineering 6, no. 3 (March 1, 2020): 264–74. https://doi.org/10.1016/j.eng.2020.01.007.

Song, L., F. Chen, Y. Zhuo, X. Qian, H. Li, and Y. Chen. “AccPar: Tensor partitioning for heterogeneous deep learning accelerators.” In Proceedings - 2020 IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, 342–55, 2020. https://doi.org/10.1109/HPCA47549.2020.00036.

Li, B., J. R. Doppa, P. P. Pande, K. Chakrabarty, J. X. Qiu, and H. H. Li. “3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.” ACM Journal on Emerging Technologies in Computing Systems 16, no. 2 (January 29, 2020). https://doi.org/10.1145/3375699.

Xu, Y., Y. Li, S. Zhang, W. Wen, B. Wang, Y. Qi, Y. Chen, W. Lin, and H. Xiong. “TRP: Trained rank pruning for efficient deep neural networks.” In IJCAI International Joint Conference on Artificial Intelligence, 2021-January:977–83, 2020.

Song, L., F. Chen, Y. Chen, and H. H. Li. “Parallelism in Deep Learning Accelerators.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2020-January:645–50, 2020. https://doi.org/10.1109/ASP-DAC47756.2020.9045206.