Publications

Hai, L., and C. Yiran. “An overview of non-volatile memory technology and the implication for tools and architectures.” In Proceedings -Design, Automation and Test in Europe, DATE, 731–36, 2009.

Li, H., H. Xi, Y. Chen, J. Stricklin, X. Wang, and T. Zhang. “Thermal-assisted spin transfer torque memory (STT-RAM) cell design exploration.” In Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009, 217–22, 2009. https://doi.org/10.1109/ISVLSI.2009.17.

Koh, C. K., W. F. Wong, Y. Chen, and H. Li. “Tolerating process variations in large, set-associative caches: The buddy cache.” Transactions on Architecture and Code Optimization 6, no. 2 (June 1, 2009). https://doi.org/10.1145/1543753.1543757.

Xi, H., X. Wang, Y. Chen, and P. J. Ryan. “Ordering of magnetic nanoparticles in bilayer structures.” Journal of Physics D: Applied Physics 42, no. 1 (April 8, 2009). https://doi.org/10.1088/0022-3727/42/1/015006.

Wang, X., Y. Chen, H. Xi, H. Li, and D. Dimitrov. “Spintronic memristor through spin-thorque-induced magnetization motion.” IEEE Electron Device Letters 30, no. 3 (February 12, 2009): 294–97. https://doi.org/10.1109/LED.2008.2012270.

Sun, G., X. Dong, Y. Xie, J. Li, and Y. Chen. “A novel architecture of the 3D stacked MRAM L2 Cache for CMPs.” In Proceedings - International Symposium on High-Performance Computer Architecture, 239–49, 2009. https://doi.org/10.1109/HPCA.2009.4798259.

Xu, W., Y. Chen, X. Wang, and T. Zhang. “Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.” In Proceedings - Design Automation Conference, 87–90, 2009. https://doi.org/10.1145/1629911.1629936.

Xu, W., T. Zhang, and Y. Chen. “Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin.” In Proceedings - IEEE International Symposium on Circuits and Systems, 1898–1901, 2008. https://doi.org/10.1109/ISCAS.2008.4541813.

Dong, X., X. Wu, G. Sun, Y. Xie, H. Li, and Y. Chen. “Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement.” In Proceedings - Design Automation Conference, 554–59, 2008. https://doi.org/10.1109/DAC.2008.4555878.

Chen, Y., X. Wang, H. Li, H. Liu, and D. V. Dimitrov. “Design margin exploration of Spin-Torque Transfer RAM (SPRAM).” In Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008, 684–90, 2008. https://doi.org/10.1109/ISQED.2008.4479820.

Li, H., Y. Chen, and S. Jamshidi. “Design for Low Power.” In The Computer Engineering Handbook, Second Edition - 2 Volume Set. CRC Press, 2008.

Wang, X., Y. Chen, H. Li, D. Dimitrov, and H. Liu. “Spin torque random access memory down to 22 nm technology.” IEEE Transactions on Magnetics 44, no. 11 PART 2 (January 1, 2008): 2479–82. https://doi.org/10.1109/TMAG.2008.2002386.

Chen, Yiran, Xiaobin Wang, Hai Li, Harry Liu, and Dimitar V. Dimitrov. “Design margin exploration of spin-torque transfer RAM (SPRAM).” In ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 684–90. IEEE COMPUTER SOC, 2008. https://doi.org/10.1109/ISQED.2008.140.

Chen, Y., H. Li, J. Li, and C. K. Koh. “Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI.” In Proceedings of the International Symposium on Low Power Electronics and Design, 195–200, 2007. https://doi.org/10.1145/1283780.1283822.

Wong, W. F., C. K. Kon, Y. Chen, and H. Li. “VOSCH: Voltage scaled cache hierarchies.” In 2007 IEEE International Conference on Computer Design, ICCD 2007, 496–503, 2007. https://doi.org/10.1109/ICCD.2007.4601944.

Li, H., C. K. Koh, V. Balakrishnan, and Y. Chen. “Statistical timing analysis considering spatial correlations.” In Proceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007, 102–7, 2007. https://doi.org/10.1109/ISQED.2007.149.

Li, H., Y. Chen, K. Roy, and C. K. Koh. “SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 2006:158–63, 2006.

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Cascaded carry-select adder (C² SA): A new structure for low-power CSA design.” In Proceedings of the International Symposium on Low Power Electronics and Design, 115–18, 2005.

Kang, D., Y. Chen, and K. Roy. “Power supply noise-aware scheduling and allocation for DSP synthesis.” In Proceedings - International Symposium on Quality Electronic Design, ISQED, 48–53, 2005. https://doi.org/10.1109/ISQED.2005.97.

Li, H., C. Y. Cher, K. Roy, and T. N. Vijaykumar. “Combined circuit and architectural level variable supply-voltage scaling for low power.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 5 (May 1, 2005): 564–75. https://doi.org/10.1109/TVLSI.2005.844295.

Chen, Y. R., H. Li, K. Roy, and C. K. Koh. “Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 775–78. IEEE, 2005.

Lam, W. C. D., J. Jain, C. K. Koh, V. Balakrishnan, and Y. Chen. “Statistical based link insertion for robust clock network design.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2005:588–91, 2005. https://doi.org/10.1109/ICCAD.2005.1560134.

Chen, Y., H. Li, K. Roy, and C. K. Koh. “Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies.” In Proceedings of the Custom Integrated Circuits Conference, 2005:775–78, 2005. https://doi.org/10.1109/CICC.2005.1568783.

Chen, Y., K. Roy, and C. K. Koh. “Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 1 (January 1, 2005): 75–85. https://doi.org/10.1109/TVLSI.2004.840404.

Chen, Y., K. Roy, and C. K. Koh. “Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 894–99, 2004.