Publications
STT-RAM cell design considering CMOS and MTJ temperature dependence." Ieee Transactions on Magnetics 48, no. 11 (2012): 3821-3824.
"STT-Ram cell design considering MTJ asymmetric switching." Spin 2, no. 3 (2012).
"STT-RAM cell optimization considering MTJ and CMOS variations." Ieee Transactions on Magnetics 47, no. 10 (2011): 2962-2965.
"Study of
η(1475)
and
." Physical Review D 97, no. 5 (2018).
"A Survey of Accelerator Architectures for Deep Neural Networks." Engineering 6, no. 3 (2020): 264-274.
"A survey of architectures of neural network accelerators." Scientia Sinica Informationis 52, no. 4 (2022): 596-611.
"Survey of low-power electric vehicles: A design automation perspective." Ieee Design & Test 35, no. 6 (2018): 44-70.
"A synapse memristor model with forgetting effect." Physics Letters A 377, no. 45-48 (2013): 3260-3265.
"Thread batching for high-performance energy-efficient GPU memory design." Acm Journal on Emerging Technologies in Computing Systems 15, no. 4 (2019).
"Thwarting Replication Attack against Memristor-Based Neuromorphic Computing System." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 10 (2020): 2192-2205.
"A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 12 (2016): 2008-2017.
"Tolerating process variations in large, set-associative caches: The buddy cache." Acm Transactions on Architecture and Code Optimization 6, no. 2 (2009): 1-34.
"Toward Efficient and Adaptive Design of Video Detection System with Deep Neural Networks." Acm Transactions on Embedded Computing Systems 21, no. 3 (2022).
"TPrune: Efficient Transformer Pruning for Mobile Devices." Acm Transactions on Cyber Physical Systems 5, no. 3 (2021).
"Training memristor-based multilayer neuromorphic networks with SGD, momentum and adaptive learning rates." Neural Networks : the Official Journal of the International Neural Network Society 128 (2020): 142-149.
"Training SAR-ATR Models for Reliable Operation in Open-World Environments." Ieee Journal of Selected Topics in Applied Earth Observations and Remote Sensing 14 (2021): 3954-3966.
"TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 10 (2018): 1985-1998.
"User classification and authentication for mobile device based on gesture recognition." Advances in Information Security 55 (2014): 125-135.
"Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (2010): 1621-1624.
"VD-GAN: A Unified Framework for Joint Prototype and Representation Learning from Contaminated Single Sample per Person." Ieee Transactions on Information Forensics and Security 16 (2021): 2246-2259.
"A visually secure image encryption scheme based on compressive sensing." Signal Processing 134 (2017): 35-51.
"Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement." Spin 02, no. 03 (2012): 1240008.
"Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (2012): 2020-2030.
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