Publications

Sun, M., L. E. Burke, Z. H. Mao, Y. Chen, H. C. Chen, Y. Bai, Y. Li, C. Li, and W. Jia. “Ebutton: A wearable computer for health monitoring and personal assistance.” In Proceedings Design Automation Conference, 2014. https://doi.org/10.1145/2593069.2596678.

Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” IEEE Transactions on Very Large Scale Integration VLSI Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.

Li, X., S. Duan, L. Wang, T. Huang, and Y. Chen. “Memristive radial basis function neural network for parameters adjustment of PID controller.” In Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics, 8866:150–58, 2014. https://doi.org/10.1007/978-3-319-12436-0_17.

Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies Design Architecture and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.

Wang, D., J. Guo, K. Bu, and Y. Chen. “Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.” In 2014 International Conference on Computing Networking and Communications Icnc 2014, 259–63, 2014. https://doi.org/10.1109/ICCNC.2014.6785342.

Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 126–31. IEEE, 2014.

Wen, W., Y. Zhang, M. Mao, and Y. Chen. “STT-RAM reliability enhancement through ECC and access scheme optimization.” In Proceedings of the International Symposium on Consumer Electronics ISCE, 2014. https://doi.org/10.1109/ISCE.2014.6884324.

Li, B., Y. Wang, Y. Chen, H. H. Li, and H. Yang. “ICE: Inline calibration for memristor crossbar-based computing engine.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.197.

Chen, L., C. Li, T. Huang, H. G. Ahmad, and Y. Chen. “A phenomenological memristor model for short-term/long-term memory.” Physics Letters Section A General Atomic and Solid State Physics 378, no. 40 (January 1, 2014): 2924–30. https://doi.org/10.1016/j.physleta.2014.08.018.

Nixon, K. W., X. Chen, H. Zhou, Y. Liu, and Y. Chen. “Mobile GPU power consumption reduction via dynamic resolution and frame rate scaling.” In 6th Workshop on Power Aware Computing and Systems Hotpower 2014, 2014.

Dong, Zhekang, Shukai Duan, Xiaofang Hu, Lidan Wang, and Hai Li. “A novel memristive multilayer feedforward small-world neural network with its applications in PID control.” TheScientificWorldJournal 2014 (January 2014): 394828. https://doi.org/10.1155/2014/394828.

Bu, K., Y. R. Chen, H. Xu, W. Yi, and Q. Y. Xie. “NAND flash service lifetime estimate with recovery effect and retention time relaxation.” Journal of Central South University 21, no. 8 (January 1, 2014): 3205–13. https://doi.org/10.1007/s11771-014-2292-x.

Park, E., S. Yoo, S. Lee, and H. Li. “Accelerating graph computation with racetrack memory and pointer-assisted graph representation.” In Proceedings Design Automation and Test in Europe Date, 2014. https://doi.org/10.7873/DATE2014.172.

Zhang, C., G. Sun, P. Li, T. Wang, D. Niu, and Y. Chen. “SBAC: A statistics based cache bypassing method for asymmetric-access caches.” In Proceedings of the International Symposium on Low Power Electronics and Design, 345–50, 2014. https://doi.org/10.1145/2627369.2627611.

Chen, X., K. W. Nixon, H. Zhou, Y. Liu, and Y. Chen. “FingerShadow: An OLED power optimization based on smartphone touch interactions.” In 6th Workshop on Power Aware Computing and Systems Hotpower 2014, 2014.

Chen, L., C. Li, T. Huang, Y. Chen, S. Wen, and J. Qi. “A synapse memristor model with forgetting effect.” Physics Letters Section A General Atomic and Solid State Physics 377, no. 45–48 (December 17, 2013): 3260–65. https://doi.org/10.1016/j.physleta.2013.10.024.

Wang, J., Y. Tim, W. F. Wong, and H. H. Li. “A practical low-power memristor-based analog neural branch predictor.” In Proceedings of the International Symposium on Low Power Electronics and Design, 175–80, 2013. https://doi.org/10.1109/ISLPED.2013.6629290.

Li, B., Y. Shan, M. Hu, Y. Wang, Y. Chen, and H. Yang. “Memristor-based approximated computation.” In Proceedings of the International Symposium on Low Power Electronics and Design, 242–47, 2013. https://doi.org/10.1109/ISLPED.2013.6629302.

Chen, Q., Q. Qiu, H. Li, and Q. Wu. “A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 202–5, 2013. https://doi.org/10.1109/ICCAD.2013.6691119.

Zhang, Y., I. Bayram, Y. Wang, H. Li, and Y. Chen. “ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 9–16, 2013. https://doi.org/10.1109/ICCAD.2013.6691091.

Jones, A. K., Y. Chen, W. O. Collinge, H. Xu, L. A. Schaefer, A. E. Landis, and M. M. Bilec. “Considering fabrication in sustainable computing.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 206–10, 2013. https://doi.org/10.1109/ICCAD.2013.6691120.

Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.

Wen, W., M. Mao, X. Zhu, S. H. Kang, D. Wang, and Y. Chen. “CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.” In IEEE ACM International Conference on Computer Aided Design Digest of Technical Papers Iccad, 1–8, 2013. https://doi.org/10.1109/ICCAD.2013.6691090.

Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.

Li, J., L. Shi, Q. Li, C. J. Xue, Y. Chen, Y. Xu, and W. Wang. “Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.” ACM Transactions on Design Automation of Electronic Systems 19, no. 1 (December 1, 2013). https://doi.org/10.1145/2534393.