Publications

Found 625 results
[ Type(Desc)] Year
Conference Paper
R Joshi, R Kanj, P Wang, and HH Li. "Universal Statistical Cure For Predicting Memory Loss (Invited Paper)." In 2012 Ieee/Acm International Conference on Computer Aided Design (Iccad), 236-239. 2011.
X Bi, M Mao, D Wang, and H Li. "Unleashing the potential of MLC STT-RAM caches." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 429-436. 2013.
M Inkawhich, N Inkawhich, E Davis, H Li, and Y Chen. "The Untapped Potential of Off-the-Shelf Convolutional Neural Networks." In Proceedings 2022 Ieee/Cvf Winter Conference on Applications of Computer Vision, Wacv 2022, 2907-2916. 2022.
Z Shao, Y Liu, Y Chen, and T Li. "Utilizing PCM for energy optimization in embedded systems." In Proceedings 2012 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2012, 398-403. 2012.
Y Chen, H Li, J Li, and CK Koh. "Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI." In Proceedings of the International Symposium on Low Power Electronics and Design, 195-200. 2007.
Z Sun, H Li, Y Chen, and X Wang. "Variation tolerant sensing scheme of spin-transfer torque memory for yield improvement." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 432-437. 2010.
Z Qin, Z Xu, Q Dong, Y Chen, and X Chen. "VoCaM: Visualization oriented convolutional neural network acceleration on mobile system: Invited paper." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 835-840. Vol. 2017-November. 2017.
B Liu, H Li, Y Chen, X Li, Q Wu, and T Huang. "Vortex: Variation-aware training for memristor X-bar." In Proceedings Design Automation Conference. Vol. 2015-July. 2015.
WF Wong, CK Kon, Y Chen, and H Li. "VOSCH: Voltage scaled cache hierarchies." In 2007 Ieee International Conference on Computer Design, Iccd 2007, 496-503. 2007.
H Li, CY Cher, TN Vijaykumar, and K Roy. "VSV: L2-miss-driven variable supply-voltage scaling for low power." In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 19-28. Vol. 2003-January. 2003.
M Mao, J Hu, Y Chen, and H Li. "VWS: A versatile warp scheduler for exploring diverse cache localities of GPGPU applications." In Proceedings Design Automation Conference. Vol. 2015-July. 2015.
C Liu, and H Li. "A weighted sensing scheme for ReRAM-based cross-point memory array." In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 65-70. 2014.
BT Cline, S Heinrich-Barna, PJ Wright, H Li, V Viswanath, S Hu, P Wesling, G Qu, S Ghosh, and AA Iranmanesh. "Welcome." In Proceedings International Symposium on Quality Electronic Design, Isqed. 2017.
B Cline, S Mukhopadhyay, PJ Wright, H Li, V Viswanath, P Wesling, G Qu, and A Iranmanesh. "Welcome." In Isqed. 2016.
PJ Wright, A Raychowdhury, B Liu, S Mukhopadhyay, HH Li, AA Iranmanesh, SM Alam, and P Wesling. "Welcome to ISQED 2015." In Proceedings International Symposium on Quality Electronic Design, Isqed. Vol. 2015-April. 2015.
B Cline, HH Li, G Qu, S Mukhopadhyay, V Viswanath, AA Iranmanesh, PJ Wright, and P Wesling. "WELCOME to ISQED 2016." In Proceedings International Symposium on Quality Electronic Design, Isqed. Vol. 2016-May. 2016.
F Chen, L Song, HH Li, and Y Chen. "ZARA: A novel zero-free dataflow accelerator for generative adversarial networks in 3D ReRAM." In Proceedings Design Automation Conference. 2019.
Journal Article
Y Chen, H Li, X Wang, W Zhu, W Xu, and T Zhang. "A 130 nm 1.2 V/3.3 v 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme." Ieee Journal of Solid State Circuits 47, no. 2 (2012): 560-573.
Y Chen. "2020: Looking Forward to the Next Decade [From the Editor]." Ieee Circuits and Systems Magazine 20, no. 1 (2020).
Y Chen. "2021: The Greatest Reset [From the Editor]." Ieee Circuits and Systems Magazine 21, no. 1 (2021).
YC Chen, HH Li, W Zhang, and RE Pino. "The 3-D stacking bipolar RRAM for high density." Ieee Transactions on Nanotechnology 11, no. 5 (2012): 948-956.
B Li,, PP Pande, K Chakrabarty, JX Qiu, and HH Li. "3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks." Acm Journal on Emerging Technologies in Computing Systems 16, no. 2 (2020).
C Ogbogu, AI Arka, BK Joardar,, H Li, K Chakrabarty, and PP Pande. "Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 41, no. 11 (2022): 3626-3637.
BK Joardar,, PP Pande, H Li, and K Chakrabarty. "AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 40, no. 5 (2021): 971-984.
C Song, HP Cheng, H Yang, S Li, C Wu, Q Wu, and H Li. "Adversarial Attack: A New Threat to Smart Devices and How to Defend It." Ieee Consumer Electronics Magazine 9, no. 4 (2020): 49-55.

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