|Title||STT-RAM reliability enhancement through ECC and access scheme optimization|
|Publication Type||Conference Paper|
|Year of Publication||2014|
|Authors||W Wen, Y Zhang, M Mao, and Y Chen|
|Conference Name||Proceedings of the International Symposium on Consumer Electronics, Isce|
Multi-level cell Spin-Transfer Torque RAM (MLC STT-RAM) greatly suffers from the significantly degraded operation reliability and high programming cost. In this paper, a novel MLC design, namely ternary-state MLC (TS-MLC STT-RAM), is proposed for high-reliable high-performance memory systems by leveraging a cross-layer solution set. Based on the structure, several circuit and architecture schemes are proposed to enhance both the reliability and access latency of the memory cells. © 2014 IEEE.