STT-Ram cell design considering MTJ asymmetric switching

As one promising candidate for next-generation nonvolatile memory technologies, spin-transfer torque random access memory (STT-RAM) has demonstrated many attractive features, such as nanosecond access time, high integration density, nonvolatility, and good CMOS process compatibility. In this paper, we address the asymmetry in the write operations of STT-RAM cells: the mean and the deviation of the write latency for the switching from low- to high-resistance state is much longer or larger than that of the opposite direction. Some special design concerns, e.g., the data-dependent write reliability, are raised by this observation. We systematically analyze the root reasons for the asymmetric switching of MTJs, including the thermal-induced statistical MTJ magnetization process, the asymmetric biasing condition of NMOS transistors, and the device variations of both NMOS and MTJ. Their impacts on STT-RAM write operations were also investigated. At last, we explore the design spaces of different STT-RAM cell structures by considering the asymmetry of write operations.