Nonpersistent errors optimization in spin-MOS logic and storage circuitry

TitleNonpersistent errors optimization in spin-MOS logic and storage circuitry
Publication TypeJournal Article
Year of Publication2011
AuthorsP Wang, X Wang, Y Zhang, H Li, SP Levitan, and Y Chen
JournalIeee Transactions on Magnetics
Start Page3860
Pagination3860 - 3863
Date Published01/2011

By combining the flexibility of MOS logic and the nonvolatility of spintronic devices, Spin-MOS logic and storage circuitries offer a promising approach to implement a highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitries suffers from additional nonpersistent error that incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. In this work, we quantitatively investigate the impacts of the thermal fluctuations on the operations of two typical Spin-MOS circuitries: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile flip-flop design. The possible design techniques to reduce thermal incurred nonpersistent error rate are also discussed. Our experimental results show that the optimization of nonpersistent and persistent errors are closely entangled with each other and should be conducted from both circuit design and magnetic device engineering perspectives simultaneously. © 2011 IEEE.

Short TitleIeee Transactions on Magnetics