Improving STT MRAM storage density through smaller-than-worst-case transistor sizing

TitleImproving STT MRAM storage density through smaller-than-worst-case transistor sizing
Publication TypeConference Paper
Year of Publication2009
AuthorsW Xu, Y Chen, X Wang, and T Zhang
Conference NameProceedings Design Automation Conference
Date Published01/2009
Abstract

This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic tunneling junction (MTJ) write current threshold variability. In conventional design practice, the nMOS transistor within each memory cell is sized to be large enough to carry a current larger than the worst-case MTJ write current threshold, leading to an increasing storage density penalty as the technology scales down. To mitigate such variability-induced storage density penalty, this paper presents a smaller-than-worst-case transistor sizing approach with the underlying theme of jointly considering memory cell transistor sizing and defect tolerance. Its effectiveness is demonstrated using 256Mb STT MRAM design at 45nm node as a test vehicle. Results show that, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design practice. Copyright 2009 ACM.

DOI10.1145/1629911.1629936