|Title||Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies|
|Publication Type||Conference Paper|
|Year of Publication||2005|
|Authors||Y Chen, H Li, K Roy, and CK Koh|
|Conference Name||Proceedings of the Custom Integrated Circuits Conference|
A novel on-chip Decoupling Capacitor (Decap) design - Gated Decoupling Capacitor (GDecap) - is proposed to minimize the leakage power dissipation associated with present-day on-chip decoupling capacitors. Experiments on the application of GDecap in an 8-way clock-gated cluster pipeline show that on average, 41.7% Decap leakage power is improved, with only 0.037% worst-case performance degradation, at 70nm technology node. Around 5.36% area overhead in Decap area is incurred, compared to the conventional Decap deployment. © 2005 IEEE.