|Title||An FPGA design framework for CNN sparsification and acceleration|
|Publication Type||Conference Paper|
|Year of Publication||2017|
|Authors||S Li, W Wen, Y Wang, S Han, Y Chen, and HH Li|
|Conference Name||Proceedings Ieee 25th Annual International Symposium on Field Programmable Custom Computing Machines, Fccm 2017|
Convolutional neural networks (CNNs) have recently broken many performance records in image recognition and object detection problems. The success of CNNs, to a great extent, is enabled by the fast scaling-up of the networks that learn from a huge volume of data. The deployment of big CNN models can be both computation-intensive and memory-intensive, leaving severe challenges to hardware implementations. In recent years, sparsification techniques that prune redundant connections in the networks while still retaining the similar accuracy emerge as promising solutions to alliterate the computation overheads associated with CNNs .