|Title||Emerging memristor technology enabled next generation cortical processor|
|Publication Type||Conference Paper|
|Year of Publication||2014|
|Authors||H Li, M Hu, X Liu, M Mao, C Li, and S Duan|
|Conference Name||International System on Chip Conference|
The explosion of 'big data' applications imposes severe challenges of data processing speed and scalability on traditional computer systems. However, the performance of von Neumann machine is greatly hindered by the increasing performance gap between CPU and memory ('known as memory wall'), motivating the active research on new or alternative computing architecture. As one important instance, neuromorphic computing systems have gained considerable attentions. Neuromorphic computing systems refer to the computing architecture inspired by the working mechanism of human brains. The human neocortex system naturally possesses a massively parallel architecture with closely coupled memory and computing as well as the unique analog domain operations. By imitating such structure, neuromorphic computing system is anticipated to be superior to the conventional computer systems in image recognition and natural language understanding. Among all the possible solutions, cortical processor has gained significant attention. The cortical-like hierarchical model conducts data processing by using spatial and temporal evolution of the data representation to form relationships. The straightforward hardware realization of such massively parallel algorithms inspired by cortical models, however, commonly consumes a large volume of memory and computing resources, incurring high design complexity and hardware cost. Here, we suggest realizing the cortical processor by combining the flexibility of conventional architecture in computation and the efficiency of the emerging memristor technology. Computing accelerator is introduced to accelerate neuromorphic computations with ultra-low energy consumption. The computation and data exchange are carefully coordinated and supported by a hierarchical network-on-chip across digital and analog domains.