|Title||Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies|
|Publication Type||Journal Article|
|Year of Publication||2010|
|Authors||Y Chen, X Wang, H Li, H Xi, Y Yan, and W Zhu|
|Journal||Ieee Transactions on Very Large Scale Integration (Vlsi) Systems|
|Pagination||1724 - 1734|
We propose a magnetic and electric level spin-transfer torque random access memory (STT-RAM) cell model to simulate the write operation of an STT-RAM. The model of a magnetic tunneling junction (MTJ) is modified to take into account the electrical response of the MOS transistor that is connected to the MTJ. A dynamic design flow is also proposed to minimize any unnecessary design margin in an STT-RAM cell design by leveraging from the new STT-RAM cell model. The design of an STT-RAM cell with a one-transistor-one-MTJ (1T1J) structure shows that our technique can reduce more than 22% of the STT-RAM cell area, compared with a conventional STT-RAM cell model at a TSMC 90-nm technology node. The performance and the reliability of the memory cell were unaffected. By using our model, we analyzed the scalability of STT-RAM technology down to a 22-nm Bulk-CMOS technology node. The tradeoffs among the MTJ switching current, the thermal stability of the MTJ and the MOS transistor driving strength are discussed. Some magnetic- and circuit-level solutions to achieve 9F2 STT-RAM cell area at 22-nm technology node are also discussed. © 2009 IEEE.
|Short Title||Ieee Transactions on Very Large Scale Integration (Vlsi) Systems|