|Title||Design and Data Management for Magnetic Racetrack Memory|
|Publication Type||Conference Paper|
|Year of Publication||2018|
|Authors||B Li, F Chen, W Kang, W Zhao, Y Chen, and H Li|
|Conference Name||Proceedings Ieee International Symposium on Circuits and Systems|
Benefiting from its ultra-high storage density, high energy efficiency, and non-volatility, racetrack memory demonstrates great potential in replacing conventional SRAM as large on-chip memory. Integrating the tape-like racetrack memory, however, faces unique design challenges from cell structure to architecture design. This paper reviews some cross-layer design methodologies for racetrack memory as on-chip cache hierarchy. Research studies show that with proper architectural design and data management, racetrack memory can achieve significant area reduction, system performance enhancement, and energy saving compared to state-of-the-art memory technologies.