DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design

TitleDCG: Deterministic Clock-Gating for Low-Power Microprocessor Design
Publication TypeJournal Article
Year of Publication2004
AuthorsH Li, S Bhunia, Y Chen, K Roy, and TN Vijaykumar
JournalIeee Transactions on Very Large Scale Integration (Vlsi) Systems
Volume12
Start Page245
Issue3
Pagination245 - 254
Date Published03/2004
Abstract

With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Because clock power can be significant in high-performance processors, we propose a deterministic clock-gating (DCG) technique which effectively reduces clock power. DCG is based on the key observation that for many of the pipelined stages of a modern processor, the circuit block usage in the near future is known a few cycles ahead of time. Our experiments show an average of 19.9% reduction in processor power with virtually no performance loss for an eight-issue, out-of-order superscalar by applying DCG to execution units, pipeline latches, D-cache wordline decoders, and result bus drivers.

DOI10.1109/TVLSI.2004.824307
Short TitleIeee Transactions on Very Large Scale Integration (Vlsi) Systems