Title | Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors |
Publication Type | Journal Article |
Year of Publication | 2005 |
Authors | Y Chen, K Roy, and CK Koh |
Journal | Ieee Transactions on Very Large Scale Integration (Vlsi) Systems |
Volume | 13 |
Issue | 1 |
Start Page | 75 |
Pagination | 75 - 85 |
Date Published | 01/2005 |
Abstract | In this paper, we propose an integrated architectural and physical planning approach to minimize the current surge in high-performance clock-gated microprocessors. In our approach, we use priority assignment optimization (PAO) and dynamic functional unit (FU) selection (DFS) to balance current demand in the floorplan. Two complementary methods - FU ordering with submodule design and issue pattern management - are also proposed to enhance the above techniques. Experimental results show that at the 0.18-μm technology node, the PAO can reduce the peak noise by 11.75% and consequently, the decoupling capacitance (Decap) requirement by 24.22% without any degradation in instructions per cycle (IPC). Moreover, an enhanced DFS reduces the peak noise by 13.39% as well as Decap requirement by 29.58%. Experiments at the 90-nm technology node show that our methodology can further reduce the peak noise and the Decap requirement by 16.57% and 44.85% with PAO, or 18.16% and 47.58% with DFS. We also show that our approach does not increase the clock period for 0.18-μm technology and beyond. |
DOI | 10.1109/TVLSI.2004.840404 |
Short Title | Ieee Transactions on Very Large Scale Integration (Vlsi) Systems |