Publications

2014

Li, X., S. Duan, L. Wang, T. Huang, and Y. Chen. “Memristive radial basis function neural network for parameters adjustment of PID controller.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 8866:150–58, 2014. https://doi.org/10.1007/978-3-319-12436-0_17.

Sun, Z., X. Bi, H. Li, W. F. Wong, and X. Zhu. “STT-RAM cache hierarchy with multiretention MTJ designs.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, no. 6 (January 1, 2014): 1281–93. https://doi.org/10.1109/TVLSI.2013.2267754.

Li, H., Z. Sun, X. Bi, W. F. Wong, X. Zhu, and W. Wu. “STT-RAM cache hierarchy design and exploration with emerging magnetic devices.” In Emerging Memory Technologies: Design, Architecture, and Applications, 9781441995513:169–99, 2014. https://doi.org/10.1007/978-1-4419-9551-3_7.

Wang, D., J. Guo, K. Bu, and Y. Chen. “Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system.” In 2014 International Conference on Computing, Networking and Communications, ICNC 2014, 259–63, 2014. https://doi.org/10.1109/ICCNC.2014.6785342.

Wen, W., Y. Zhang, M. Mao, and Y. Chen. “STT-RAM reliability enhancement through ECC and access scheme optimization.” In Proceedings of the International Symposium on Consumer Electronics, ISCE, 2014. https://doi.org/10.1109/ISCE.2014.6884324.

Wang, Jianxing, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, and Hai Helen Li. “Optimizing MLC-based STT-RAM Caches by Dynamic Block Size Reconfiguration.” In 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD), 126–31. IEEE, 2014.

2013

Chen, L., C. Li, T. Huang, Y. Chen, S. Wen, and J. Qi. “A synapse memristor model with forgetting effect.” Physics Letters, Section A: General, Atomic and Solid State Physics 377, no. 45–48 (December 17, 2013): 3260–65. https://doi.org/10.1016/j.physleta.2013.10.024.

Wang, J., Y. Tim, W. F. Wong, and H. H. Li. “A practical low-power memristor-based analog neural branch predictor.” In Proceedings of the International Symposium on Low Power Electronics and Design, 175–80, 2013. https://doi.org/10.1109/ISLPED.2013.6629290.

Li, B., Y. Shan, M. Hu, Y. Wang, Y. Chen, and H. Yang. “Memristor-based approximated computation.” In Proceedings of the International Symposium on Low Power Electronics and Design, 242–47, 2013. https://doi.org/10.1109/ISLPED.2013.6629302.

Ji, F., H. H. Li, B. Wysocki, C. Thiem, and N. McDonald. “Memristor-based synapse design and a case study in reconfigurable systems.” In Proceedings of the International Joint Conference on Neural Networks, 2013. https://doi.org/10.1109/IJCNN.2013.6706776.

Wen, Shiping, Gang Bao, Zhigang Zeng, Yiran Chen, and Tingwen Huang. “Global exponential synchronization of memristor-based recurrent neural networks with time-varying delays.” Neural Networks : The Official Journal of the International Neural Network Society 48 (December 2013): 195–203. https://doi.org/10.1016/j.neunet.2013.10.001.

Chen, Q., Q. Qiu, H. Li, and Q. Wu. “A neuromorphic architecture for anomaly detection in autonomous large-area traffic monitoring.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 202–5, 2013. https://doi.org/10.1109/ICCAD.2013.6691119.

Zhang, Y., I. Bayram, Y. Wang, H. Li, and Y. Chen. “ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 9–16, 2013. https://doi.org/10.1109/ICCAD.2013.6691091.

Jones, A. K., Y. Chen, W. O. Collinge, H. Xu, L. A. Schaefer, A. E. Landis, and M. M. Bilec. “Considering fabrication in sustainable computing.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 206–10, 2013. https://doi.org/10.1109/ICCAD.2013.6691120.

Bi, X., M. Mao, D. Wang, and H. Li. “Unleashing the potential of MLC STT-RAM caches.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 429–36, 2013. https://doi.org/10.1109/ICCAD.2013.6691153.

Wen, W., M. Mao, X. Zhu, S. H. Kang, D. Wang, and Y. Chen. “CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 1–8, 2013. https://doi.org/10.1109/ICCAD.2013.6691090.

Li, Y., Y. Zhang, H. Li, Y. Chen, and A. K. Jones. “C1C: A configurable, compiler-guided STT-RAM L1 cache.” Transactions on Architecture and Code Optimization 10, no. 4 (December 1, 2013). https://doi.org/10.1145/2555289.2555308.

Li, J., L. Shi, Q. Li, C. J. Xue, Y. Chen, Y. Xu, and W. Wang. “Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh.” ACM Transactions on Design Automation of Electronic Systems 19, no. 1 (December 1, 2013). https://doi.org/10.1145/2534393.

Chen, Z., L. Zhang, X. Bi, and H. Li. “A pseudo-weighted sensing scheme for memristor based cross-point memory.” In Proceedings of the 2013 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2013, 38–39, 2013. https://doi.org/10.1109/NanoArch.2013.6623039.

Wen, S., Z. Zeng, T. Huang, and Y. Chen. “Fuzzy modeling and synchronization of different memristor-based chaotic circuits.” Physics Letters, Section A: General, Atomic and Solid State Physics 377, no. 34–36 (November 1, 2013): 2016–21. https://doi.org/10.1016/j.physleta.2013.05.046.

Chen, Y., W. F. Wong, H. Li, C. K. Koh, Y. Zhang, and W. Wen. “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.” ACM Journal on Emerging Technologies in Computing Systems 9, no. 2 (October 21, 2013). https://doi.org/10.1145/2463585.2463592.

Hu, M., H. Li, Y. Chen, Q. Wu, and G. S. Rose. “BSB training scheme implementation on memristor-based circuit.” In Proceedings of the 2013 IEEE Symposium on Computational Intelligence for Security and Defense Applications, CISDA 2013 - 2013 IEEE Symposium Series on Computational Intelligence, SSCI 2013, 80–87, 2013. https://doi.org/10.1109/CISDA.2013.6595431.

Wen, S., Z. Zeng, T. Huang, and Y. Chen. “Passivity analysis of memristor-based recurrent neural networks with time-varying delays.” Journal of the Franklin Institute 350, no. 8 (October 1, 2013): 2354–70. https://doi.org/10.1016/j.jfranklin.2013.05.026.

Zhao, B., J. Yang, Y. Zhang, Y. Chen, and H. Li. “Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.” ACM Transactions on Design Automation of Electronic Systems 18, no. 4 (October 1, 2013). https://doi.org/10.1145/2500459.

Zhang, Y., L. Zhang, and Y. Chen. “MLC STT-RAM design considering probabilistic and asymmetric MTJ switching.” In Proceedings - IEEE International Symposium on Circuits and Systems, 113–16, 2013. https://doi.org/10.1109/ISCAS.2013.6571795.