Publications

2015

Tang, T., R. Luo, B. Li, H. Li, Y. Wang, and H. Yang. “Energy efficient spiking neural network design with RRAM devices.” In Proceedings of the 14th International Symposium on Integrated Circuits, ISIC 2014, 268–71, 2015. https://doi.org/10.1109/ISICIR.2014.7029565.

Liu, B., H. Li, Y. Chen, X. Li, T. Huang, Q. Wu, and M. Barnell. “Reduction and IR-drop compensations techniques for reliable neuromorphic computing systems.” In IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2015-January:63–70, 2015. https://doi.org/10.1109/ICCAD.2014.7001330.

Wang, Yu-ying, Long-biao He, Hai-jiang Zhu, and Ping Yang. “CONSISTENCY OF SURFACE PULSE AND RECIPROCITY CALIBRATION OF PIEZOELECTRIC AE SENSORS.” In PROCEEDINGS OF THE 2015 SYMPOSIUM ON PIEZOELECTRICITY, ACOUSTIC WAVES AND DEVICE APPLICATIONS, edited by X. Tao, X. Zhao, C. Wang, and F. Yu, 189–92. IEEE, 2015.

Chen, L., C. Li, T. Huang, S. Wen, and Y. Chen. “Memristor crossbar array for image storing.” In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 9377 LNCS:166–73, 2015. https://doi.org/10.1007/978-3-319-25393-0_19.

Wang, P., E. Eken, W. Zhang, R. Joshi, R. Kanj, and Y. Chen. “A thermal and process variation aware MTJ switching model and its applications in soft error analysis.” In More than Moore Technologies for Next Generation Computer Design, 101–25, 2015. https://doi.org/10.1007/978-1-4939-2163-8_5.

Wen, W., Y. Zhang, and Y. Chen. “Statistical reliability/energy characterization in STT-RAM cell designs.” In Spintronics-Based Computing, 201–30, 2015. https://doi.org/10.1007/978-3-319-15180-9_7.

2014

Qiu, Q., Z. Li, K. Ahmed, H. H. Li, and M. Hu. “Neuromorphic acceleration for context aware text image recognition.” In IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation, 2014. https://doi.org/10.1109/SiPS.2014.6986098.

Wang, J., P. Roy, W. F. Wong, X. Bi, and H. Li. “Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.” In 2014 32nd IEEE International Conference on Computer Design, ICCD 2014, 133–38, 2014. https://doi.org/10.1109/ICCD.2014.6974672.

Li, H., M. Hu, X. Liu, M. Mao, C. Li, and S. Duan. “Emerging memristor technology enabled next generation cortical processor.” In International System on Chip Conference, 377–82, 2014. https://doi.org/10.1109/SOCC.2014.6948958.

Chen, Y., J. Guo, and Z. Sun. “CPU-GPU system designs for high performance cloud computing.” In High Performance Cloud Auditing and Applications, 9781461432968:283–99, 2014. https://doi.org/10.1007/978-1-4614-3296-8_11.

Eken, E., Y. Zhang, W. Wen, R. Joshi, H. Li, and Y. Chen. “A novel self-reference technique for STT-RAM read and write reliability enhancement.” IEEE Transactions on Magnetics 50, no. 11 (November 1, 2014). https://doi.org/10.1109/TMAG.2014.2323196.

Wen, W., Y. Zhang, Y. Chen, Y. Wang, and Y. Xie. “PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, no. 11 (November 1, 2014): 1644–56. https://doi.org/10.1109/TCAD.2014.2351581.

Bayram, I., and Y. Chen. “NV-TCAM: Alternative interests and practices in NVM designs.” In 2014 IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2014, 2014. https://doi.org/10.1109/NVMSA.2014.6927206.

Pan, C., M. Xie, J. Hu, Y. Chen, and C. Yang. “3M-PCM: Exploiting multiple write modes MLC phase change main memory in embedded systems.” In 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2014, 2014. https://doi.org/10.1145/2656075.2656076.

Hu, Miao, Hai Li, Yiran Chen, Qing Wu, Garrett S. Rose, and Richard W. Linderman. “Memristor crossbar-based neuromorphic computing system: a case study.” IEEE Transactions on Neural Networks and Learning Systems 25, no. 10 (October 2014): 1864–78. https://doi.org/10.1109/tnnls.2013.2296777.

Li, H., M. Hu, C. Li, and S. Duan. “Memristor modeling - Static, statistical, and stochastic methodologies.” In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 406–11, 2014. https://doi.org/10.1109/ISVLSI.2014.108.

Liu, C., and H. Li. “A weighted sensing scheme for ReRAM-based cross-point memory array.” In Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 65–70, 2014. https://doi.org/10.1109/ISVLSI.2014.32.

Hu, X., G. Feng, H. Li, Y. Chen, and S. Duan. “An adjustable memristor model and its application in small-world neural networks.” In Proceedings of the International Joint Conference on Neural Networks, 7–14, 2014. https://doi.org/10.1109/IJCNN.2014.6889605.

Chen, L., C. Li, T. Huang, X. He, H. Li, and Y. Chen. “STDP learning rule based on memristor with STDP property.” In Proceedings of the International Joint Conference on Neural Networks, 1–6, 2014. https://doi.org/10.1109/IJCNN.2014.6889506.

Zhang, Y., W. Wen, H. Li, and Y. Chen. “The Prospect of STT-RAM Scaling.” In Metallic Spintronic Devices. CRC Press, 2014.

Chen, L., C. Li, T. Huang, Y. Chen, and X. Wang. “Memristor crossbar-based unsupervised image learning.” Neural Computing and Applications 25, no. 2 (August 1, 2014): 393–400. https://doi.org/10.1007/s00521-013-1501-0.

Chen, Y., H. Li, and Z. Sun. “Spintronic memristor as interface between DNA and solid state devices.” In Memristors and Memristive Systems, 9781461490685:281–98, 2014. https://doi.org/10.1007/978-1-4614-9068-5_9.

Chen, Ying, Peng Liu, and Zhi Wu Yu. “Research on the Sol-Gel Method of Preparing Ternary Nano SiO2-Al2O3-TiO2 Materials.” In Key Engineering Materials, 609–610:281–87. Trans Tech Publications, Ltd., 2014. https://doi.org/10.4028/www.scientific.net/kem.609-610.281.

Hu, M., Y. Wang, Q. Qiu, Y. Chen, and H. Li. “The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 831–36, 2014. https://doi.org/10.1109/ASPDAC.2014.6742993.

Wang, J., Y. Tim, W. F. Wong, Z. L. Ong, Z. Sun, and H. H. Li. “A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 610–15, 2014. https://doi.org/10.1109/ASPDAC.2014.6742958.