Publications

Wen, W., C. Wu, Y. Wang, Y. Chen, and H. Li. “Learning structured sparsity in deep neural networks.” In Advances in Neural Information Processing Systems, 2082–90, 2016.

Chen, Y., H. Li, Y. Xie, and D. Niu. “Components, Platforms, and Architectures: Low-Power Design of Emerging Memory Technologies.” In Handbook of Energy-Aware and Green Computing-Two Volume Set, 1:67–90, 2016.

Cline, Brian, Saibal Mukhopadhyay, Peter J. Wright, Hai Li, Vinod Viswanath, Paul Wesling, Gang Qu, and Ali Iranmanesh. “Welcome.” In ISQED. IEEE, 2016.

Zhang, X., G. Sun, C. Zhang, W. Zhang, Y. Liang, T. Wang, Y. Chen, and J. Di. “Fork path: Improving efficiency of ORAM by removing redundant memory accesses.” In Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 05-09-December-2015:102–14, 2015. https://doi.org/10.1145/2830772.2830787.

Li, B., P. Gu, Y. Shan, Y. Wang, Y. Chen, and H. Yang. “RRAM-Based Analog Approximate Computing.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 12 (December 1, 2015): 1905–17. https://doi.org/10.1109/TCAD.2015.2445741.

Liang, H., Y. C. Chen, T. Luo, W. Zhang, H. Li, and B. He. “Hierarchical Library Based Power Estimator for Versatile FPGAs.” In Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, 25–32, 2015. https://doi.org/10.1109/MCSoC.2015.44.

Li, Z., C. Liu, Y. Wang, B. Yan, C. Yang, J. Yang, and H. Li. “An overview on memristor crossabr based neuromorphic circuit and architecture.” In IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 2015-October:52–56, 2015. https://doi.org/10.1109/VLSI-SoC.2015.7314391.

Liang, H., W. Zhang, S. Sinha, Y. C. Chen, and H. Li. “Hierarchical library based power estimator for versatile FPGAs.” In 25th International Conference on Field Programmable Logic and Applications, FPL 2015, 2015. https://doi.org/10.1109/FPL.2015.7293969.

Chen, Y., K. Choi, and W. Zhao. “Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.” IEEE Transactions on Multi-Scale Computing Systems 1, no. 3 (September 1, 2015): 125–26. https://doi.org/10.1109/TMSCS.2015.2505118.

Li, H. H., C. Liu, B. Yan, C. Yang, L. Song, Z. Li, Y. Chen, W. Zhu, Q. Wu, and H. Jiang. “Spiking-based matrix computation by leveraging memristor crossbar array.” In 2015 IEEE Symposium on Computational Intelligence for Security and Defense Applications, CISDA 2015 - Proceedings, 43–46, 2015. https://doi.org/10.1109/CISDA.2015.7208626.

Li, Q., Y. He, J. Li, L. Shi, Y. Chen, and C. J. Xue. “Compiler-assisted refresh minimization for volatile STT-RAM cache.” IEEE Transactions on Computers 64, no. 8 (August 1, 2015): 2169–81. https://doi.org/10.1109/TC.2014.2360527.

Li, H., B. Liu, X. Liu, M. Mao, Y. Chen, Q. Wu, and Q. Qiu. “The applications of memristor devices in next-generation cortical processor designs.” In Proceedings - IEEE International Symposium on Circuits and Systems, 2015-July:17–20, 2015. https://doi.org/10.1109/ISCAS.2015.7168559.

Li, Z., B. Yan, L. Yang, W. Zhao, Y. Chen, and H. Li. “A new self-reference sensing scheme for TLC MRAM.” In Proceedings - IEEE International Symposium on Circuits and Systems, 2015-July:593–96, 2015. https://doi.org/10.1109/ISCAS.2015.7168703.

Liu, C., B. Yan, C. Yang, L. Song, Z. Li, B. Liu, Y. Chen, H. Li, Q. Wu, and H. Jiang. “A spiking neuromorphic design with resistive crossbar.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744783.

Liu, B., C. Wu, H. Li, Y. Chen, Q. Wu, M. Barnell, and Q. Qiu. “Cloning your mind: Security challenges in cognitive system designs and their solutions.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2747915.

Mao, M., J. Hu, Y. Chen, and H. Li. “VWS: A versatile warp scheduler for exploring diverse cache localities of GPGPU applications.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744931.

Liu, X., M. Mao, B. Liu, H. Li, Y. Chen, B. Li, Y. Wang, et al. “RENO: A high-efficient reconfigurable neuromorphic computing accelerator design.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744900.

Wen, W., C. R. Wu, X. Hu, B. Liu, T. Y. Ho, X. Li, and Y. Chen. “An EDA framework for large scale hybrid neuromorphic computing systems.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744795.

Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel: A novel NAND flash storage system design for LDPC latency reduction.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744843.

Chen, X., Y. Chen, and C. J. Xue. “DaTuM: Dynamic tone mapping technique for OLED display power saving based on video classification.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744814.

Liu, B., H. Li, Y. Chen, X. Li, Q. Wu, and T. Huang. “Vortex: Variation-aware training for memristor X-bar.” In Proceedings - Design Automation Conference, Vol. 2015-July, 2015. https://doi.org/10.1145/2744769.2744930.

Li, S., C. Wu, H. Li, B. Li, Y. Wang, and Q. Qiu. “FPGA acceleration of recurrent neural network based language model.” In Proceedings - 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, 111–18, 2015. https://doi.org/10.1109/FCCM.2015.50.

Eken, E., Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. “Spin-hall assisted STT-RAM design and discussion.” In 2015 IEEE International Magnetics Conference, INTERMAG 2015, 2015. https://doi.org/10.1109/INTMAG.2015.7156644.

Gu, S., E. H. M. Sha, Q. Zhuge, Y. Chen, and J. Hu. “Area and performance co-optimization for domain wall memory in application-specific embedded systems.” In Proceedings - Design Automation Conference, Vol. 2015-June, 2015. https://doi.org/10.1145/2744769.2744800.

Zhang, Y., B. Yan, W. Kang, Y. Cheng, J. O. Klein, Y. Chen, and W. Zhao. “Compact model of subvolume MTJ and its design application at nanoscale technology nodes.” IEEE Transactions on Electron Devices 62, no. 6 (June 1, 2015): 2048–55. https://doi.org/10.1109/TED.2015.2414721.