An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks

TitleAn Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks
Publication TypeJournal Article
Year of Publication2021
AuthorsB Kim, E Hanson, and H Li
JournalIeee Transactions on Circuits and Systems Ii: Express Briefs
Volume68
Start Page1600
Issue5
Pagination1600 - 1604
Date Published05/2021
Abstract

Convolutional neural networks (CNNs) have been evolving with tremendous success in visual recognition, obtaining human-level accuracy. The conventional hardware architecture, however, is facing difficulty in realizing real-time and energy-efficient operations on CNN. To efficiently operate CNN algorithms on the hardware, researchers are actively studying processing-in-memory (PIM) with resistive random-access memory (ReRAM). Digital PIM is particularly attractive because analog designs struggle with undesirable device properties and require additional circuits like analog-to-digital converter and digital-to-analog converter. However, the massive area originated from digital PIM is a hindrance to its applications. In this work, we present a three-dimensional (3D) ReRAM convolution logic processor design to tackle the limitation of digital PIM. At the hardware level, we leverage 3D ReRAM to take advantage of its area efficiency. The design simplicity without accuracy loss is accomplished by exploiting binarized weight networks (BWNs) at the algorithm level. Specifically, our 3D ReRAM processor computes the convolution of BWN based on a presumed full adder and a split-half addition scheme, which are proposed in this brief to maximize resource consumption efficiency. As a result, the proposed design achieves 3.7times to 5.7times and 5times to 42.5times area- and time-saving according to the bit precision in comparison to the original digital PIM.

DOI10.1109/TCSII.2021.3067840
Short TitleIeee Transactions on Circuits and Systems Ii: Express Briefs