Publications

Found 605 results
Type [ Year(Desc)]
2002
A Agarwal, H Li, and K Roy. "DRG-Cache: A data retention gated-ground cache for low power." In Proceedings Design Automation Conference, 473-478. 2002.
S Bhunia, H Li, and K Roy. "A high performance IDDQ testable cache for scaled CMOS technologies." In Proceedings of the Asian Test Symposium, 157-162. Vol. 2002-January. 2002.
Y Chen, V Balakrishnan, CK Koh, and K Roy. "Model reduction in the time-domain using Laguerre polynomials and Krylov methods." In Proceedings Design, Automation and Test in Europe, Date, 931-936. 2002.
2003
H Li, S Bhunia, Y Chen, TN Vijaykumar, and K Roy. "Deterministic clock gating for microprocessor power reduction." In Proceedings International Symposium on High Performance Computer Architecture, 113-122. Vol. 12. 2003.
Y Chen, K Roy, and CK Koh. "Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-gated Microprocessors." In Proceedings of the International Symposium on Low Power Electronics and Design, 229-234. 2003.
A Agarwal, H Li, and K Roy. "A single-Vt low-leakage gated-ground cache for deep submicron." Ieee Journal of Solid State Circuits 38, no. 2 (2003): 319-328.
H Li, CY Cher, TN Vijaykumar, and K Roy. "VSV: L2-miss-driven variable supply-voltage scaling for low power." In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 19-28. Vol. 2003-January. 2003.
2004
H Li, S Bhunia, Y Chen, K Roy, and TN Vijaykumar. "DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (2004): 245-254.
Y Chen, K Roy, and CK Koh. "Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 894-899. 2004.
2005
Y Chen,, K Roy, and. "Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design." In Islped '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005., 115-118. 2005.
Y Chen, H Li, K Roy, and CK Koh. "Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design." In Proceedings of the International Symposium on Low Power Electronics and Design, 115-118. 2005.
H Li, CY Cher, K Roy, and TN Vijaykumar. "Combined circuit and architectural level variable supply-voltage scaling for low power." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (2005): 564-575.
Y Chen, K Roy, and CK Koh. "Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 1 (2005): 75-85.
YR Chen, H Li, K Roy, CK Koh, and. "Gated decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies." In CICC: PROCEEDINGS OF THE IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 775-778. 2005.
Y Chen, H Li, K Roy, and CK Koh. "Gated Decap: Gate leakage control of on-chip decoupling capacitors in scaled technologies." In Proceedings of the Custom Integrated Circuits Conference, 775-778. Vol. 2005. 2005.
D Kang, Y Chen, and K Roy. "Power supply noise-aware scheduling and allocation for DSP synthesis." In Proceedings International Symposium on Quality Electronic Design, Isqed, 48-53. 2005.
WCD Lam, J Jain, CK Koh, V Balakrishnan, and Y Chen. "Statistical based link insertion for robust clock network design." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 588-591. Vol. 2005. 2005.
2006
H Li, Y Chen, K Roy, and CK Koh. "SAVS: A self-adaptive variable supply-voltage technique for process- Tolerant and power-efficient multi-issue superscalar processor design." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 158-163. Vol. 2006. 2006.
2007
H Li, CK Koh, V Balakrishnan, and Y Chen. "Statistical timing analysis considering spatial correlations." In Proceedings Eighth International Symposium on Quality Electronic Design, Isqed 2007, 102-107. 2007.
Y Chen, H Li, J Li, and CK Koh. "Variable-latency adder (VL-adder): New arithmetic circuit design practice to overcome NBTI." In Proceedings of the International Symposium on Low Power Electronics and Design, 195-200. 2007.
WF Wong, CK Kon, Y Chen, and H Li. "VOSCH: Voltage scaled cache hierarchies." In 2007 Ieee International Conference on Computer Design, Iccd 2007, 496-503. 2007.
2008
X Dong, X Wu, G Sun, Y Xie, H Li, and Y Chen. "Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement." In Proceedings Design Automation Conference, 554-559. 2008.
Y Chen, X Wang, H Li, H Liu, and DV Dimitrov. "Design margin exploration of Spin-Torque Transfer RAM (SPRAM)." In Proceedings of the 9th International Symposium on Quality Electronic Design, Isqed 2008, 684-690. 2008.
X Wang, Y Chen, H Li, D Dimitrov, and H Liu. "Spin torque random access memory down to 22 nm technology." Ieee Transactions on Magnetics 44, no. 11 PART 2 (2008): 2479-2482.

Pages