Found 600 results
[ Type(Asc)] Year
Journal Article
Z Sun, H Li, Y Chen, and X Wang. "Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (2012): 2020-2030.
HH Li, and Z Sun. "Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement." Spin 02, no. 03 (2012): 1240008.
X Chai, Z Gan, Y Chen, and Y Zhang. "A visually secure image encryption scheme based on compressive sensing." Signal Processing 134 (2017): 35-51.
M Pang, B Wang, YM Cheung, Y Chen, and B Wen. "VD-GAN: A Unified Framework for Joint Prototype and Representation Learning from Contaminated Single Sample per Person." Ieee Transactions on Information Forensics and Security 16 (2021): 2246-2259.
Y Chen, H Li, CK Koh, J Li, K Roy, G Sun, and Y Xie. "Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 11 (2010): 1621-1624.
KW Nixon, Y Chen, ZH Mao, and K Li. "User classification and authentication for mobile device based on gesture recognition." Advances in Information Security 55 (2014): 125-135.
Z Liu, M Mao, T Liu, X Wang, W Wen, Y Chen, H Li, D Wang, Y Pei, and N Ge. "TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 37, no. 10 (2018): 1985-1998.
NA Inkawhich, EK Davis, MJ Inkawhich, UK Majumder, and Y Chen. "Training SAR-ATR Models for Reliable Operation in Open-World Environments." Ieee Journal of Selected Topics in Applied Earth Observations and Remote Sensing 14 (2021): 3954-3966.
Z Yan, J Chen, R Hu, T Huang, Y Chen, and S Wen. "Training memristor-based multilayer neuromorphic networks with SGD, momentum and adaptive learning rates." Neural Networks : the Official Journal of the International Neural Network Society 128 (2020): 142-149.
J Mao, H Yang, A Li, H Li, and Y Chen. "TPrune: Efficient Transformer Pruning for Mobile Devices." Acm Transactions on Cyber Physical Systems 5, no. 3 (2021).
J Mao, Q Yang, A Li, KW Nixon, H Li, and Y Chen. "Toward Efficient and Adaptive Design of Video Detection System with Deep Neural Networks." Acm Transactions on Embedded Computing Systems 21, no. 3 (2022).
CK Koh, WF Wong, Y Chen, and H Li. "Tolerating process variations in large, set-associative caches: The buddy cache." Acm Transactions on Architecture and Code Optimization 6, no. 2 (2009): 1-34.
S Gu, EHM Sha, Q Zhuge, Y Chen, and J Hu. "A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 35, no. 12 (2016): 2008-2017.
C Yang, B Liu, H Li, Y Chen, M Barnell, Q Wu, W Wen, and J Rajendran. "Thwarting Replication Attack against Memristor-Based Neuromorphic Computing System." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 10 (2020): 2192-2205.
B Li, M Mao, X Liu, T Liu, Z Liu, W Wen, Y Chen, and HH Li. "Thread batching for high-performance energy-efficient GPU memory design." Acm Journal on Emerging Technologies in Computing Systems 15, no. 4 (2019).
L Chen, C Li, T Huang, Y Chen, S Wen, and J Qi. "A synapse memristor model with forgetting effect." Physics Letters A 377, no. 45-48 (2013): 3260-3265.
N Chang, MA Faruque, Z Shao, CJ Xue, Y Chen, and D Baek. "Survey of low-power electric vehicles: A design automation perspective." Ieee Design & Test 35, no. 6 (2018): 44-70.
Y Chen, and Y Wang. "A survey of architectures of neural network accelerators." Scientia Sinica Informationis 52, no. 4 (2022): 596-611.
Y Chen, Y Xie, L Song, F Chen, and T Tang. "A Survey of Accelerator Architectures for Deep Neural Networks." Engineering 6, no. 3 (2020): 264-274.
M Ablikim, MN Achasov, S Ahmed, O Albayrak, M Albrecht, M Alekseev, DJ Ambrose, A Amoroso, FF An, Q An et al. "Study of η(1475) and ." Physical Review D 97, no. 5 (2018).
Y Zhang, X Wang, H Li, and Y Chen. "STT-RAM cell optimization considering MTJ and CMOS variations." Ieee Transactions on Magnetics 47, no. 10 (2011): 2962-2965.
Y Zhang, W Wen, and Y Chen. "STT-Ram cell design considering MTJ asymmetric switching." Spin 2, no. 3 (2012).
X Bi, H Li, and X Wang. "STT-RAM cell design considering CMOS and MTJ temperature dependence." Ieee Transactions on Magnetics 48, no. 11 (2012): 3821-3824.
Z Sun, X Bi, H Li, WF Wong, and X Zhu. "STT-RAM cache hierarchy with multiretention MTJ designs." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (2014): 1281-1293.