Publications
RRAM-Based Analog Approximate Computing." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 34, no. 12 (2015): 1905-1917.
"Shift-Optimized Energy-Efficient Racetrack-Based Main Memory." Journal of Circuits, Systems and Computers 27, no. 05 (2018): 1850081.
"A single-Vt low-leakage gated-ground cache for deep submicron." Ieee Journal of Solid State Circuits 38, no. 2 (2003): 319-328.
"Sliding mode control of neural networks via continuous or periodic sampling event-triggering algorithm." Neural Networks : the Official Journal of the International Neural Network Society 121 (2020): 140-147.
"Sliding Mode Stabilization of Memristive Neural Networks With Leakage Delays and Control Disturbance." Ieee Transactions on Neural Networks and Learning Systems 32, no. 3 (2021): 1254-1263.
"Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition." Neural Computing and Applications 27, no. 4 (2016): 837-844.
"Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 41, no. 10 (2022): 3479-3491.
"SpikeSen: Low-latency In-sensor-intelligence Design with Neuromorphic Spiking Neurons." Ieee Transactions on Circuits and Systems Ii: Express Briefs (2023): 1.
"Spin torque random access memory down to 22 nm technology." Ieee Transactions on Magnetics 44, no. 11 PART 2 (2008): 2479-2482.
"Spin transfer torque memory with thermal assist mechanism: A case study." Ieee Transactions on Magnetics 46, no. 3 PART 2 (2010): 860-865.
"SPINBIS: Spintronics-based Bayesian inference system with stochastic computing." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 39, no. 4 (2020): 789-802.
"Spintronic Memristor as Interface between DNA and Solid State Devices." Ieee Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (2016): 212-221.
"Spintronic memristor: Compact model and statistical analysis." Journal of Low Power Electronics 7, no. 2 (2011): 234-244.
"Spintronic memristor temperature sensor." Ieee Electron Device Letters 31, no. 1 (2010): 20-22.
"Spintronic memristor through spin-thorque-induced magnetization motion." Ieee Electron Device Letters 30, no. 3 (2009): 294-297.
"Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation." Iet Computers & Digital Techniques 5, no. 3 (2011): 213-220.
"Statistical Cache Bypassing for Non-Volatile Memory." Ieee Transactions on Computers 65, no. 11 (2016): 3427-3440.
"STT-RAM cache hierarchy with multiretention MTJ designs." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (2014): 1281-1293.
"STT-RAM cell design considering CMOS and MTJ temperature dependence." Ieee Transactions on Magnetics 48, no. 11 (2012): 3821-3824.
"STT-Ram cell design considering MTJ asymmetric switching." Spin 2, no. 3 (2012).
"STT-RAM cell optimization considering MTJ and CMOS variations." Ieee Transactions on Magnetics 47, no. 10 (2011): 2962-2965.
"Study of
η(1475)
and
." Physical Review D 97, no. 5 (2018).
"A Survey of Accelerator Architectures for Deep Neural Networks." Engineering 6, no. 3 (2020): 264-274.
"A survey of architectures of neural network accelerators." Scientia Sinica Informationis 52, no. 4 (2022): 596-611.
"Survey of low-power electric vehicles: A design automation perspective." Ieee Design & Test 35, no. 6 (2018): 44-70.
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