Publications
Performance, power, and reliability tradeoffs of STT-RAM cell subject to architecture-level requirement." Ieee Transactions on Magnetics 47, no. 10 (2011): 2356-2359.
"Processor caches built using multi-level spin-transfer torque RAM cells." In Proceedings of the International Symposium on Low Power Electronics and Design, 73-78. 2011.
"Spintronic memristor: Compact model and statistical analysis." Journal of Low Power Electronics 7, no. 2 (2011): 234-244.
"Stacking magnetic random access memory atop microprocessors: An architecture-level evaluation." Iet Computers & Digital Techniques 5, no. 3 (2011): 213-220.
"STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 471-477. 2011.
"STT-RAM cell optimization considering MTJ and CMOS variations." Ieee Transactions on Magnetics 47, no. 10 (2011): 2962-2965.
"Universal statistical cure for predicting memory loss." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 236-239. 2011.
"Universal Statistical Cure For Predicting Memory Loss (Invited Paper)." In 2012 Ieee/Acm International Conference on Computer Aided Design (Iccad), 236-239. 2011.
"Access scheme of multi-level cell spin-transfer torque random access memory and its optimization." In 2007 50th Midwest Symposium on Circuits and Systems, 1109-1112. 2010.
"The application of spintronic devices in magnetic bio-sensing." In Proceedings of the 2nd Asia Symposium on Quality Electronic Design, Asqed 2010, 230-234. 2010.
"Applications of TMR devices in solid state circuits and systems." In 2010 International Soc Design Conference, Isocc 2010, 252-255. 2010.
"Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM." In Proceedings of the International Symposium on Low Power Electronics and Design, 1-6. 2010.
"Compact model of memristors and its application in computing systems." In Proceedings Design, Automation and Test in Europe, Date, 673-678. 2010.
"Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (2010): 1724-1734.
"Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search Speed." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 1 (2010): 66-74.
"Emerging non-volatile memory technologies: From materials, to device, circuit, and architecture." In 2007 50th Midwest Symposium on Circuits and Systems, 1-4. 2010.
"A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement." In Proceedings International Symposium on High Performance Computer Architecture. 2010.
"Impact of process variations on emerging memristor." In Proceedings Design Automation Conference, 877-882. 2010.
"Low-power dual-element memristor based memory design." In Proceedings of the International Symposium on Low Power Electronics and Design, 25-30. 2010.
"Nondestructive Self-Reference Scheme for Spin-Transfer Torque Random Access Memory (STT-RAM)." In Design, Automation and Test in Europe Conference and Exhibition , IEEE, 148-153. 2010.
"A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)." In Proceedings Design, Automation and Test in Europe, Date, 148-153. 2010.
"Patents relevant to cross-point memory array." Recent Patents on Electrical Engineeringe 3, no. 2 (2010): 114-124.
"Patents relevant to spintronic memristor." Recent Patents on Electrical Engineeringe 3, no. 1 (2010): 10-18.
"PCMO device with high switching stability." Ieee Electron Device Letters 31, no. 8 (2010): 866-868.
"Scalability of PCMO-based resistive switch device in DSM technologies." In Proceedings of the 11th International Symposium on Quality Electronic Design, Isqed 2010, 327-332. 2010.
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