Publications
] "Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices." In Proceedings Design Automation Conference, 1000-1005. 2012.
"A software approach for combating asymmetries of non-volatile memories." In Proceedings of the International Symposium on Low Power Electronics and Design, 191-196. 2012.
"Spintronic devices: From memory to memristor." In Icsict 2012 2012 Ieee 11th International Conference on Solid State and Integrated Circuit Technology, Proceedings. 2012.
"Spintronic memristor based temperature sensor design with CMOS current reference." In Proceedings Design, Automation and Test in Europe, Date, 1301-1306. 2012.
"Statistical memristor modeling and case study in neuromorphic computing." In Proceedings Design Automation Conference, 585-590. 2012.
"STT-RAM cell design considering CMOS and MTJ temperature dependence." Ieee Transactions on Magnetics 48, no. 11 (2012): 3821-3824.
"STT-Ram cell design considering MTJ asymmetric switching." Spin 2, no. 3 (2012).
"A thermal and process variation aware MTJ switching model and its applications in soft error analysis." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 720-727. 2012.
"uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology." In Fpt 2012 2012 International Conference on Field Programmable Technology, 80-86. 2012.
"Utilizing PCM for energy optimization in embedded systems." In Proceedings 2012 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2012, 398-403. 2012.
"Voltage driven nondestructive self-reference sensing for STT-Ram yield enhancement." Spin 02, no. 03 (2012): 1240008.
"Voltage driven nondestructive self-reference sensing scheme of spin-transfer torque memory." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 20, no. 11 (2012): 2020-2030.
"A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis." In Proceedings of the Custom Integrated Circuits Conference. 2011.
"3D-HIM: A 3D High-density interleaved memory for bipolar RRAM design." In Proceedings of the 2011 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2011, 59-64. 2011.
"3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers." In Proceedings Design, Automation and Test in Europe, Date, 583-586. 2011.
"Current switching in MgO-based magnetic tunneling junctions." Ieee Transactions on Magnetics 47, no. 1 PART 2 (2011): 156-160.
"Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 19, no. 3 (2011): 483-493.
"Emerging non-volatile memories: Opportunities and challenges." In Embedded Systems Week 2011, Esweek 2011 Proceedings of the 9th Ieee/Acm/Ifip International Conference on Hardware/Software Codesign and System Synthesis, Codes+Isss'11, 325-334. 2011.
"Emerging sensing techniques for emerging memories." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 204-210. 2011.
"Fast statistical model of TiO 2 thin-film memristor and design implication." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 345-352. 2011.
"Geometry variations analysis of TiO2 thin-film and spintronic memristors." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 25-30. 2011.
"MRAC: A memristor-based reconfigurable framework for adaptive cache replacement." In Parallel Architectures and Compilation Techniques Conference Proceedings, Pact, 207-208. 2011.
"Multi retention level STT-RAM cache designs with a dynamic refresh scheme." In Proceedings of the Annual International Symposium on Microarchitecture, Micro, 329-338. 2011.
"Nonpersistent errors optimization in spin-MOS logic and storage circuitry." Ieee Transactions on Magnetics 47, no. 10 (2011): 3860-3863.