Publications

Found 617 results
Type [ Year(Asc)]
2012
X Chen, B Liu, Y Chen, M Zhao, CJ Xue, and X Guo. "Active compensation technique for the thin-film transistor variations and OLED aging of mobile device displays." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 516-522. 2012.
X Bi, H Li, and JJ Kim. "Analysis and optimization of thermal effect on STT-RAM based 3-D stacked cache design." In Proceedings 2012 Ieee Computer Society Annual Symposium on Vlsi, Isvlsi 2012, 374-379. 2012.
B Zhao, J Yang, Y Zhang, Y Chen, and H Li. "Architecting a common-source-line array for bipolar non-volatile memory devices." In Proceedings Design, Automation and Test in Europe, Date, 1451-1454. 2012.
Y Zhang, X Wang, Y Li, AK Jones, and Y Chen. "Asymmetry of MTJ switching and its implication to STT-RAM designs." In Proceedings Design, Automation and Test in Europe, Date, 1313-1318. 2012.
B Liu, Y Chen, B Wysocki, and T Huang. "The circuit realization of a neuromorphic computing system with memristor-based synapse design." In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 357-365. Vol. 7663 LNCS. 2012.
Y Li, Y Zhang, Y Chen, and AK Jones. "Combating write penalties using software dispatch for on-chip MRAM integration." Ieee Embedded Systems Letters 4, no. 4 (2012): 82-85.
H Wang, A Megill, K He, A Kirkwood, and H-K Lee. "Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity." Neural Plasticity 2012 (2012): 1-24.
Z Sun, H Li, and W Wu. "A dual-mode architecture for fast-switching STT-RAM." In Proceedings of the International Symposium on Low Power Electronics and Design, 45-50. 2012.
X Chen, J Zeng, Y Chen, W Zhang, and H Li. "Fine-grained dynamic voltage scaling on OLED display." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 807-812. 2012.
M Hu, H Li, Q Wu, and GS Rose. "Hardware realization of BSB recall function using memristor crossbar arrays." In Proceedings Design Automation Conference, 498-503. 2012.
G Sun, Y Zhang, Y Wang, and Y Chen. "Improving energy efficiency of write-asymmetric memories by log style write." In Proceedings of the International Symposium on Low Power Electronics and Design, 173-178. 2012.
YC Chen, W Zhang, and H Li. "A look up table design with 3D bipolar RRAMs." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 73-78. 2012.
Z Sun, H Li, and X Wang. "Magnetic tunnel junction design margin exploration for self-reference sensing scheme." Journal of Applied Physics 111, no. 7 (2012): 7C726-7C7263.
M Hu, H Li, Q Wu, GS Rose, and Y Chen. "Memristor crossbar based hardware realization of BSB recall function." In Proceedings of the International Joint Conference on Neural Networks. 2012.
H Wang, H Li, and RE Pino. "Memristor-based synapse design and training scheme for neuromorphic computing architecture." In Proceedings of the International Joint Conference on Neural Networks. 2012.
Y Chen, X Chen, M Zhao, and CJ Xue. "Mobile devices user-The subscriber and also the publisher of real-time OLED display power management plan." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 687-690. 2012.
Y Zhang, L Zhang, W Wen, G Sun, and Y Chen. "Multi-level cell STT-RAM: Is it realistic or just a dream?" In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 526-532. 2012.
YC Chen, W Wang, H Li, and W Zhang. "Non-volatile 3D stacking RRAM-based FPGA." In Proceedings 22nd International Conference on Field Programmable Logic and Applications, Fpl 2012, 367-372. 2012.
Z Sun, X Chen, Y Zhang, H Li, and Y Chen. "Nonvolatile memories as the data storage system for implantable ecg recorder." Acm Journal on Emerging Technologies in Computing Systems 8, no. 2 (2012): 1-16.
YC Chen, H Li, and W Zhang. "A novel peripheral circuit for RRAM-based LUT." In Iscas 2012 2012 Ieee International Symposium on Circuits and Systems, 1811-1814. 2012.
Y Chen, Y Zhang, and P Wang. "Probabilistic design in spintronic memory and logic circuit." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 323-328. 2012.
X Bi, Z Sun, H Li, and W Wu. "Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 88-94. 2012.
Z Sun, X Bi, and H Li. "Process variation aware data management for STT-RAM cache design." In Proceedings of the International Symposium on Low Power Electronics and Design, 179-184. 2012.
Y Zhang, W Wen, and Y Chen. "The prospect of STT-RAM scaling from readability perspective." Ieee Transactions on Magnetics 48, no. 11 (2012): 3035-3038.
W Wen, Y Zhang, Y Chen, Y Wang, and Y Xie. "PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method." In Proceedings Design Automation Conference, 1191-1196. 2012.

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