Publications

Found 556 results
[ Type(Desc)] Year
Conference Paper
W Wen, M Mao, X Zhu, SH Kang, D Wang, and Y Chen. "CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 1-8. 2013.
M Xie, C Pan, J Hu, C Yang, and Y Chen. "Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units." In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 316-321. 2015.
X Dong, X Wu, G Sun, Y Xie, H Li, and Y Chen. "Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement." In Proceedings Design Automation Conference, 554-559. 2008.
B Liu, Y Chen, B Wysocki, and T Huang. "The circuit realization of a neuromorphic computing system with memristor-based synapse design." In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 357-365. Vol. 7663 LNCS. 2012.
Y Wang, W Wen, L Song, and H Li. "Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 776-781. 2017.
B Liu, C Wu, H Li, Y Chen, Q Wu, M Barnell, and Q Qiu. "Cloning your mind: Security challenges in cognitive system designs and their solutions." In Proceedings Design Automation Conference. Vol. 2015-July. 2015.
B Yan, J Yang, Q Wu, Y Chen, and H Li. "A closed-loop design to enhance weight stability of memristor based neural network chips." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 541-548. Vol. 2017-November. 2017.
J Wang, Y Tim, WF Wong, ZL Ong, Z Sun, and HH Li. "A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 610-615. 2014.
Y Chen, H Li, X Wang, W Zhu, W Xu, and T Zhang. "Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM." In Proceedings of the International Symposium on Low Power Electronics and Design, 1-6. 2010.
C Wu, W Wen, T Afzal, Y Zhang, Y Chen, and HH Li. "A compact DNN: Approaching GoogLeNet-level accuracy of classification and domain adaptation." In Proceedings 30th Ieee Conference on Computer Vision and Pattern Recognition, Cvpr 2017, 761-770. Vol. 2017-January. 2017.
H Li, and M Hu. "Compact model of memristors and its application in computing systems." In Proceedings Design, Automation and Test in Europe, Date, 673-678. 2010.
Y Chen, and X Wang. "Compact modeling and corner analysis of spintronic memristor." In 2009 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2009, 7-12. 2009.
Q Li, J Li, L Shi, CJ Xue, Y Chen, and Y He. "Compiler-assisted refresh minimization for volatile STT-RAM cache." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 273-278. 2013.
C Wu, and H Li. "Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-Quality Data for Training." In Proceedings of the International Joint Conference on Neural Networks. 2020.
S Zhang, HH Li, and U Schlichtmann. "Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 107-113. 2021.
AK Jones, Y Chen, WO Collinge, H Xu, LA Schaefer, AE Landis, and MM Bilec. "Considering fabrication in sustainable computing." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 206-210. 2013.
Y-Y Wang, L-B He, H-J Zhu, and P Yang. "CONSISTENCY OF SURFACE PULSE AND RECIPROCITY CALIBRATION OF PIEZOELECTRIC AE SENSORS." In Proceedings of the 2015 Symposium on Piezoelectricity, Acoustic Waves and Device Applications, 189-192. 2015.
H Li. "Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies." In 2017 International Symposium on Vlsi Design, Automation and Test (Vlsi Dat). 2017.
W Wen, C Xu, C Wu, Y Wang, Y Chen, and H Li. "Coordinating Filters for Faster Deep Neural Networks." In Proceedings of the Ieee International Conference on Computer Vision, 658-666. Vol. 2017-October. 2017.
M Mao, H Li, AK Jones, and Y Chen. "Coordinating prefetching and STT-RAM based last-level cache management for multicore systems." In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 55-60. 2013.
Z Sun, W Wu, and H Li. "Cross-layer racetrack memory design for ultra high density and low power consumption." In Proceedings Design Automation Conference. 2013.
H Jiang, W Zhu, F Luo, K Bai, C Liu, X Zhang, JJ Yang, Q Xia, Y Chen, and Q Wu. "Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing." In Proceedings Ieee International Symposium on Circuits and Systems, 930-933. Vol. 2016-July. 2016.
J Guo, W Wen, YZ Li, S Li, H Li, and Y Chen. "DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems." In Proceedings Design, Automation and Test in Europe, Date, 380-385. 2013.
Q Yang, J Mao, Z Wang, and H Li. "DASNet: Dynamic activation sparsity for neural network efficiency improvement." In Proceedings International Conference on Tools With Artificial Intelligence, Ictai, 1401-1405. Vol. 2019-November. 2019.
S Li, Y Wang, W Wen, Y Chen, and H Li. "A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad. Vol. 07-10-November-2016. 2016.

Pages