Publications
Brain Inspired Computing: The Extraordinary Voyages in Known and Unknown Worlds." In 2021 Ieee International Symposium on Smart Electronic Systems (Ises 2021), XXXI - XXXII. 2021.
"Brain-inspired computing accelerated by memristor technology." In Proceedings of the 4th Acm International Conference on Nanoscale Computing and Communication, Nanocom 2017. 2017.
"BSB training scheme implementation on memristor-based circuit." In Proceedings of the 2013 Ieee Symposium on Computational Intelligence for Security and Defense Applications, Cisda 2013 2013 Ieee Symposium Series on Computational Intelligence, Ssci 2013, 80-87. 2013.
"BSQ: EXPLORING BIT-LEVEL SPARSITY FOR MIXED-PRECISION NEURAL NETWORK QUANTIZATION." In Iclr 2021 9th International Conference on Learning Representations. 2021.
"Build reliable and efficient neuromorphic design with memristor technology." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 224-229. 2019.
"On Building Efficient and Robust Neural Network Designs." In Conference Record Asilomar Conference on Signals, Systems and Computers, 317-321. Vol. 2022-October. 2022.
"Built-in selectors self-assembled into memristors." In Proceedings Ieee International Symposium on Circuits and Systems, 181-184. Vol. 2016-July. 2016.
"Cache coherence enabled adaptive refresh for volatile STT-RAM." In Proceedings Design, Automation and Test in Europe, Date, 1247-1250. 2013.
"Can Targeted Adversarial Examples Transfer When the Source and Target Models Have No Label Space Overlap?" In Proceedings of the Ieee International Conference on Computer Vision, 41-50. Vol. 2021-October. 2021.
"Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design." In Islped '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005., 115-118. 2005.
"Cascaded carry-select adder (C2 SA): A new structure for low-power CSA design." In Proceedings of the International Symposium on Low Power Electronics and Design, 115-118. 2005.
"Cascading Structured Pruning: Enabling High Data Reuse for Sparse DNN Accelerators." In Proceedings International Symposium on Computer Architecture, 522-535. 2022.
"CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 1-8. 2013.
"Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units." In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 316-321. 2015.
"Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement." In Proceedings Design Automation Conference, 554-559. 2008.
"The circuit realization of a neuromorphic computing system with memristor-based synapse design." In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 357-365. Vol. 7663 LNCS. 2012.
"Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 776-781. 2017.
"Cloning your mind: Security challenges in cognitive system designs and their solutions." In Proceedings Design Automation Conference. Vol. 2015-July. 2015.
"A closed-loop design to enhance weight stability of memristor based neural network chips." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 541-548. Vol. 2017-November. 2017.
"CMOS Implementation of Spiking Equilibrium Propagation for Real-Time Learning." In Proceeding Ieee International Conference on Artificial Intelligence Circuits and Systems, Aicas 2022, 283-286. 2022.
"A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 610-615. 2014.
"Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM." In Proceedings of the International Symposium on Low Power Electronics and Design, 1-6. 2010.
"A compact DNN: Approaching GoogLeNet-level accuracy of classification and domain adaptation." In Proceedings 30th Ieee Conference on Computer Vision and Pattern Recognition, Cvpr 2017, 761-770. Vol. 2017-January. 2017.
"Compact model of memristors and its application in computing systems." In Proceedings Design, Automation and Test in Europe, Date, 673-678. 2010.
"Compact modeling and corner analysis of spintronic memristor." In 2009 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2009, 7-12. 2009.
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