Publications
CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 1-8. 2013.
"Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional units." In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 316-321. 2015.
"Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement." In Proceedings Design Automation Conference, 554-559. 2008.
"The circuit realization of a neuromorphic computing system with memristor-based synapse design." In Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 357-365. Vol. 7663 LNCS. 2012.
"Classification accuracy improvement for neuromorphic computing systems with one-level precision synapses." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 776-781. 2017.
"Cloning your mind: Security challenges in cognitive system designs and their solutions." In Proceedings Design Automation Conference. Vol. 2015-July. 2015.
"A closed-loop design to enhance weight stability of memristor based neural network chips." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 541-548. Vol. 2017-November. 2017.
"A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 610-615. 2014.
"Combined magnetic-and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM." In Proceedings of the International Symposium on Low Power Electronics and Design, 1-6. 2010.
"A compact DNN: Approaching GoogLeNet-level accuracy of classification and domain adaptation." In Proceedings 30th Ieee Conference on Computer Vision and Pattern Recognition, Cvpr 2017, 761-770. Vol. 2017-January. 2017.
"Compact model of memristors and its application in computing systems." In Proceedings Design, Automation and Test in Europe, Date, 673-678. 2010.
"Compact modeling and corner analysis of spintronic memristor." In 2009 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2009, 7-12. 2009.
"Compiler-assisted refresh minimization for volatile STT-RAM cache." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 273-278. 2013.
"Conditional Transferring Features: Scaling GANs to Thousands of Classes with 30% Less High-Quality Data for Training." In Proceedings of the International Joint Conference on Neural Networks. 2020.
"Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 107-113. 2021.
"Considering fabrication in sustainable computing." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 206-210. 2013.
"CONSISTENCY OF SURFACE PULSE AND RECIPROCITY CALIBRATION OF PIEZOELECTRIC AE SENSORS." In Proceedings of the 2015 Symposium on Piezoelectricity, Acoustic Waves and Device Applications, 189-192. 2015.
"Conventional and Neuromorphic Systems Leveraging Emerging Memory Technologies." In 2017 International Symposium on Vlsi Design, Automation and Test (Vlsi Dat). 2017.
"Coordinating Filters for Faster Deep Neural Networks." In Proceedings of the Ieee International Conference on Computer Vision, 658-666. Vol. 2017-October. 2017.
"Coordinating prefetching and STT-RAM based last-level cache management for multicore systems." In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 55-60. 2013.
"Cross-layer racetrack memory design for ultra high density and low power consumption." In Proceedings Design Automation Conference. 2013.
"Cyclical sensing integrate-and-fire circuit for memristor array based neuromorphic computing." In Proceedings Ieee International Symposium on Circuits and Systems, 930-933. Vol. 2016-July. 2016.
"DA-RAID-5: A disturb aware data protection technique for NAND flash storage systems." In Proceedings Design, Automation and Test in Europe, Date, 380-385. 2013.
"DASNet: Dynamic activation sparsity for neural network efficiency improvement." In Proceedings International Conference on Tools With Artificial Intelligence, Ictai, 1401-1405. Vol. 2019-November. 2019.
"A data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad. Vol. 07-10-November-2016. 2016.
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