Publications

Found 617 results
Type [ Year(Asc)]
2014
W Wen, Y Zhang, Y Chen, Y Wang, and Y Xie. "PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 33, no. 11 (2014): 1644-1656.
D Wang, J Guo, K Bu, and Y Chen. "Reduction of data prevention cost and improvement of reliability in MLC NAND flash storage system." In 2014 International Conference on Computing, Networking and Communications, Icnc 2014, 259-263. 2014.
Y Chen, P Liu, and ZW Yu. "Research on the Sol-Gel Method of Preparing Ternary Nano SiO<sub>2</sub>-Al<sub>2</sub>O<sub>3</sub>-TiO<sub>2</sub> Materials." In Key Engineering Materials, 281-287. Vol. 609-610. 2014.
C Zhang, G Sun, P Li, T Wang, D Niu, and Y Chen. "SBAC: A statistics based cache bypassing method for asymmetric-access caches." In Proceedings of the International Symposium on Low Power Electronics and Design, 345-350. 2014.
W Wen, Y Zhang, M Mao, and Y Chen. "State-restrict MLC stt-ram designs for high-reliable high-performance memory system." In Proceedings Design Automation Conference. 2014.
L Chen, C Li, T Huang, X He, H Li, and Y Chen. "STDP learning rule based on memristor with STDP property." In Proceedings of the International Joint Conference on Neural Networks, 1-6. 2014.
X Liu, Y Li, Y Zhang, AK Jones, and Y Chen. "STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 355-360. 2014.
M Hu, Y Wang, Q Qiu, Y Chen, and H Li. "The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 831-836. 2014.
Z Sun, X Bi, H Li, WF Wong, and X Zhu. "STT-RAM cache hierarchy with multiretention MTJ designs." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 22, no. 6 (2014): 1281-1293.
W Wen, Y Zhang, M Mao, and Y Chen. "STT-RAM reliability enhancement through ECC and access scheme optimization." In Proceedings of the International Symposium on Consumer Electronics, Isce. 2014.
B Li, Y Wang, Y Weng, Y Chen, and H Yang. "Training itself: Mixed-signal training acceleration for memristor-based neural network." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 361-366. 2014.
KW Nixon, Y Chen, ZH Mao, and K Li. "User classification and authentication for mobile device based on gesture recognition." Advances in Information Security 55 (2014): 125-135.
C Liu, and H Li. "A weighted sensing scheme for ReRAM-based cross-point memory array." In Proceedings of Ieee Computer Society Annual Symposium on Vlsi, Isvlsi, 65-70. 2014.
2013
Y Zhang, I Bayram, Y Wang, H Li, and Y Chen. "ADAMS: Asymmetric differential STT-RAM cell structure for reliable and high-performance applications." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 9-16. 2013.
M Hu, H Li, Y Chen, Q Wu, and GS Rose. "BSB training scheme implementation on memristor-based circuit." In Proceedings of the 2013 Ieee Symposium on Computational Intelligence for Security and Defense Applications, Cisda 2013 2013 Ieee Symposium Series on Computational Intelligence, Ssci 2013, 80-87. 2013.
Y Li, Y Zhang, H Li, Y Chen, and AK Jones. "C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache." Acm Transactions on Architecture and Code Optimization 10, no. 4 (2013): 1-22.
Y Li, Y Zhang, H Li, Y Chen, and AK Jones. "C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache." Acm Transactions on Architecture and Code Optimization 10, no. 4 (2013): 1-22.
J Li, L Shi, Q Li, CJ Xue, Y Chen, and Y Xu. "Cache coherence enabled adaptive refresh for volatile STT-RAM." In Proceedings Design, Automation and Test in Europe, Date, 1247-1250. 2013.
W Wen, M Mao, X Zhu, SH Kang, D Wang, and Y Chen. "CD-ECC: Content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 1-8. 2013.
B Zhao, J Yang, Y Zhang, Y Chen, and H Li. "Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices." Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (2013): 1-18.
L Zhang, Z Chen, Joshua J Yang, B Wysocki, N McDonald, and Y Chen. "A compact modeling of TiO2-TiO2-x memristor." Applied Physics Letters 102, no. 15 (2013): 153503.
Q Li, J Li, L Shi, CJ Xue, Y Chen, and Y He. "Compiler-assisted refresh minimization for volatile STT-RAM cache." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 273-278. 2013.
AK Jones, Y Chen, WO Collinge, H Xu, LA Schaefer, AE Landis, and MM Bilec. "Considering fabrication in sustainable computing." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 206-210. 2013.
M Mao, H Li, AK Jones, and Y Chen. "Coordinating prefetching and STT-RAM based last-level cache management for multicore systems." In Proceedings of the Acm Great Lakes Symposium on Vlsi, Glsvlsi, 55-60. 2013.
Z Sun, W Wu, and H Li. "Cross-layer racetrack memory design for ultra high density and low power consumption." In Proceedings Design Automation Conference. 2013.

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