Publications
Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 1 (2005): 75-85.
"Current switching in MgO-based magnetic tunneling junctions." Ieee Transactions on Magnetics 47, no. 1 PART 2 (2011): 156-160.
"Data-Pattern-Aware Error Prevention Technique to Improve System Reliability." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 4 (2017): 1433-1443.
"DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (2004): 245-254.
"Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (2010): 1724-1734.
"Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 19, no. 3 (2011): 483-493.
"Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search Speed." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 1 (2010): 66-74.
"Designing pulse-coupled neural networks with spike-synchronization-dependent plasticity rule: image segmentation and memristor circuit application." Neural Computing and Applications 32, no. 17 (2020): 13441-13452.
"DisP+V: A Unified Framework for Disentangling Prototype and Variation From Single Sample per Person." Ieee Transactions on Neural Networks and Learning Systems PP (2021).
"Dynamic Regularization on Activation Sparsity for Neural Network Efficiency Improvement." Acm Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021).
"DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs." Ieee Transactions on Computers 72, no. 3 (2023): 880-892.
"Editorial for the special issue on disruptive computing technologies." Ccf Transactions on High Performance Computing 2, no. 3 (2020): 209-210.
"Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part i." Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 11 (2021): 4417-4418.
"Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part II." Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 12 (2021): 4835-4836.
"An effective image compression–encryption scheme based on compressive sensing (CS) and game of life (GOL)." Neural Computing and Applications 32, no. 17 (2020): 14113-14141.
"An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks." Ieee Transactions on Circuits and Systems Ii: Express Briefs 68, no. 5 (2021): 1600-1604.
"An efficient approach for encrypting double color images into a visually meaningful cipher image using 2D compressive sensing." Information Sciences 556 (2021): 305-340.
"An efficient chaos-based image compression and encryption scheme using block compressive sensing and elementary cellular automata." Neural Computing and Applications 32, no. 9 (2020): 4961-4988.
"Efficient neural network using pointwise convolution kernels with linear phase constraint." Neurocomputing 423 (2021): 572-579.
"An efficient visually meaningful image compression and encryption scheme based on compressive sensing and dynamic LSB embedding." Optics and Lasers in Engineering 124 (2020).
"An electroforming-free, analog interface-type memristor based on a SrFeOx epitaxial heterojunction for neuromorphic computing." Materials Today Physics 18 (2021).
"End-to-End Detection-Segmentation System for Face Labeling." Ieee Transactions on Emerging Topics in Computational Intelligence 5, no. 3 (2021): 457-467.
"Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache." Ieee Transactions on Computers 66, no. 5 (2017): 786-798.
"An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory." Ieee Transactions on Computers 66, no. 9 (2017): 1478-1490.
"ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-aware ReRAM-based In-Memory Training Systems." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems (2022): 1.
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