Publications

Found 600 results
[ Type(Desc)] Year
Journal Article
H Li, CY Cher, K Roy, and TN Vijaykumar. "Combined circuit and architectural level variable supply-voltage scaling for low power." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (2005): 564-575.
X Chai, X Zhi, Z Gan, Y Zhang, Y Chen, and J Fu. "Combining improved genetic algorithm and matrix semi-tensor product (STP) in color image encryption." Signal Processing 183 (2021).
B Zhao, J Yang, Y Zhang, Y Chen, and H Li. "Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices." Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (2013): 1-18.
SD Pyle, H Li, and RF DeMara. "Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device." Electronics Letters 52, no. 14 (2016): 1238-1240.
M Hu, Y Chen, JJ Yang, Y Wang, and H Li. "A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (2017): 1353-1366.
L Zhang, W Song, JJ Yang, H Li, and Y Chen. "A compact model for selectors based on metal doped electrolyte." Applied Physics A: Materials Science and Processing 124, no. 4 (2018).
Y Zhang, B Yan, W Kang, Y Cheng, JO Klein, Y Chen, and W Zhao. "Compact model of subvolume MTJ and its design application at nanoscale technology nodes." Ieee Transactions on Electron Devices 62, no. 6 (2015): 2048-2055.
L Zhang, Z Chen, Joshua J Yang, B Wysocki, N McDonald, and Y Chen. "A compact modeling of TiO2-TiO2-x memristor." Applied Physics Letters 102, no. 15 (2013): 153503.
Q Li, Y He, J Li, L Shi, Y Chen, and CJ Xue. "Compiler-assisted refresh minimization for volatile STT-RAM cache." Ieee Transactions on Computers 64, no. 8 (2015): 2169-2181.
H Wang, A Megill, K He, A Kirkwood, and H-K Lee. "Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity." Neural Plasticity 2012 (2012): 1-24.
X Bi, M Mao, D Wang, and H Li. "Cross-layer optimization for multilevel cell STT-RAM caches." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (2017): 1807-1820.
Y Chen, K Roy, and CK Koh. "Current demand balancing: A technique for minimization of current surge in high performance clock-gated microprocessors." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 1 (2005): 75-85.
W Zhu, H Li, Y Chen, and X Wang. "Current switching in MgO-based magnetic tunneling junctions." Ieee Transactions on Magnetics 47, no. 1 PART 2 (2011): 156-160.
J Guo, D Wang, Z Shao, and Y Chen. "Data-Pattern-Aware Error Prevention Technique to Improve System Reliability." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 4 (2017): 1433-1443.
H Li, S Bhunia, Y Chen, K Roy, and TN Vijaykumar. "DCG: Deterministic Clock-Gating for Low-Power Microprocessor Design." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 12, no. 3 (2004): 245-254.
Y Chen, X Wang, H Li, H Xi, Y Yan, and W Zhu. "Design margin exploration of spin-transfer torque RAM (STT-RAM) in scaled technologies." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 12 (2010): 1724-1734.
W Xu, H Sun, X Wang, Y Chen, and T Zhang. "Design of last-level on-chip cache using spin-torque transfer RAM (STT RAM)." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 19, no. 3 (2011): 483-493.
W Xu, T Zhang, and Y Chen. "Design of spin-torque transfer magnetoresistive RAM and CAM/TCAM with high sensing and search Speed." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 18, no. 1 (2010): 66-74.
X Xie, S Wen, Z Yan, T Huang, and Y Chen. "Designing pulse-coupled neural networks with spike-synchronization-dependent plasticity rule: image segmentation and memristor circuit application." Neural Computing and Applications 32, no. 17 (2020): 13441-13452.
M Pang, B Wang, M Ye, Y-M Cheung, Y Chen, and B Wen. "DisP+V: A Unified Framework for Disentangling Prototype and Variation From Single Sample per Person." Ieee Transactions on Neural Networks and Learning Systems PP (2021).
Q Yang, J Mao, Z Wang, and L Hai. "Dynamic Regularization on Activation Sparsity for Neural Network Efficiency Improvement." Acm Journal on Emerging Technologies in Computing Systems 17, no. 4 (2021).
E Hanson, S Li, X Qian, H Li, and Y Chen. "DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs." Ieee Transactions on Computers (2022): 1-12.
Y Chen, D Fan, Y Wang, and S Yamashita. "Editorial for the special issue on disruptive computing technologies." Ccf Transactions on High Performance Computing 2, no. 3 (2020): 209-210.
T Huang, Y Chen, Z Zeng, and L Chua. "Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part II." Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 12 (2021): 4835-4836.
T Huang, Y Chen, Z Zeng, and L Chua. "Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part i." Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 11 (2021): 4417-4418.

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