Publications
ApesNet: a pixel‐wise efficient segmentation network for embedded devices." Iet Cyber Physical Systems: Theory & Applications 1, no. 1 (2016): 78-85.
"Array Organization and Data Management Exploration in Racetrack Memory." Ieee Transactions on Computers 65, no. 4 (2016): 1041-1054.
"The bipolar and unipolar reversible behavior on the forgetting memristor model." Neurocomputing 171 (2016): 1637-1643.
"BitSystolic: A 26.7 TOPS/W 2b8b NPU with Configurable Data Flows for Edge Devices." Ieee Transactions on Circuits and Systems I: Regular Papers 68, no. 3 (2021): 1134-1145.
"Bridging a Gap in SAR-ATR: Training on Fully Synthetic and Testing on Measured Data." Ieee Journal of Selected Topics in Applied Earth Observations and Remote Sensing 14 (2021): 2942-2955.
"C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache." Acm Transactions on Architecture and Code Optimization 10, no. 4 (2013): 1-22.
"C1C: A Configurable, Compiler-Guided STT-RAM L1 Cache." Acm Transactions on Architecture and Code Optimization 10, no. 4 (2013): 1-22.
"A Case for 3D Integrated System Design for Neuromorphic Computing and AI Applications." International Journal of Semantic Computing 14, no. 4 (2020): 457-475.
"Challenges of memristor based neuromorphic computing system." Science China Information Sciences 61, no. 6 (2018).
"A chaotic image encryption algorithm based on 3-D bit-plane permutation." Neural Computing and Applications 31, no. 11 (2019): 7111-7130.
"Circuit design and exponential stabilization of memristive neural networks." Neural Networks : the Official Journal of the International Neural Network Society 63 (2015): 48-56.
"Color image compression and encryption scheme based on compressive sensing and double random encryption strategy." Signal Processing 176 (2020).
"A color image cryptosystem based on dynamic DNA encryption and chaos." Signal Processing 155 (2019): 44-62.
"Combating write penalties using software dispatch for on-chip MRAM integration." Ieee Embedded Systems Letters 4, no. 4 (2012): 82-85.
"Combined circuit and architectural level variable supply-voltage scaling for low power." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 13, no. 5 (2005): 564-575.
"Combining improved genetic algorithm and matrix semi-tensor product (STP) in color image encryption." Signal Processing 183 (2021).
"Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices." Acm Transactions on Design Automation of Electronic Systems 18, no. 4 (2013): 1-18.
"Compact low-power instant store and restore D flip-flop using a selfcomplementing spintronic device." Electronics Letters 52, no. 14 (2016): 1238-1240.
"A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks." Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems 36, no. 8 (2017): 1353-1366.
"A compact model for selectors based on metal doped electrolyte." Applied Physics A: Materials Science and Processing 124, no. 4 (2018).
"Compact model of subvolume MTJ and its design application at nanoscale technology nodes." Ieee Transactions on Electron Devices 62, no. 6 (2015): 2048-2055.
"A compact modeling of TiO2-TiO2-x memristor." Applied Physics Letters 102, no. 15 (2013): 153503.
"Compiler-assisted refresh minimization for volatile STT-RAM cache." Ieee Transactions on Computers 64, no. 8 (2015): 2169-2181.
"Consequences of inhibiting amyloid precursor protein processing enzymes on synaptic function and plasticity." Neural Plasticity 2012 (2012): 1-24.
"Cross-layer optimization for multilevel cell STT-RAM caches." Ieee Transactions on Very Large Scale Integration (Vlsi) Systems 25, no. 6 (2017): 1807-1820.
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