Publications

Chen, X., K. W. Nixon, and Y. Chen. “Practical power consumption analysis with current smartphones.” In International System on Chip Conference, 0:333–37, 2016. https://doi.org/10.1109/SOCC.2016.7905505.

Eken, E., L. Song, I. Bayram, C. Xu, W. Wen, Y. Xie, and Y. Chen. “NVSim-VX^s: An improved NVSim for variation aware STT-RAM simulation.” In Proceedings - Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2898053.

Chen, X., J. Mao, J. Gao, K. W. Nixon, and Y. Chen. “MORPh: Mobile OLED-friendly recording and playback system for low power video streaming.” In Proceedings - Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2898047.

Wen, W., C. Wu, Y. Wang, K. Nixon, Q. Wu, M. Barnell, H. Li, and Y. Chen. “A new learning method for inference accuracy, core occupation, and performance co-optimization on TrueNorth chip.” In Proceedings - Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2897968.

Chen, X., N. Khoshavi, J. Zhou, D. Huang, R. F. Demara, J. Wang, W. Wen, and Y. Chen. “AOS: Adaptive overwrite scheme for energy-efficient MLC STT-RAM cache.” In Proceedings - Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2897987.

Mao, M., W. Wen, X. Liu, J. Hu, D. Wang, Y. Chen, and H. Li. “TEMP: Thread batch enabled memory partitioning for GPU.” In Proceedings - Design Automation Conference, Vol. 05-09-June-2016, 2016. https://doi.org/10.1145/2897937.2898103.

Eken, E., I. Bayram, Y. Zhang, B. Yan, W. Wu, H. Li, and Y. Chen. “Spin-hall assisted STT-RAM design and discussion.” In Proceedings of the 18th ACM/IEEE System Level Interconnect Prediction 2016 Workshop, SLIP 2016, 2016. https://doi.org/10.1145/2947357.2947360.

Yang, J., Z. Sun, X. Wang, Y. Chen, and H. Li. “Spintronic Memristor as Interface between DNA and Solid State Devices.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 212–21. https://doi.org/10.1109/JETCAS.2016.2547700.

Hu, M., Y. Wang, W. Wen, and H. Li. “Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems.” IEEE Journal on Emerging and Selected Topics in Circuits and Systems 6, no. 2 (June 1, 2016): 235–46. https://doi.org/10.1109/JETCAS.2016.2547780.

Cline, B., H. H. Li, G. Qu, S. Mukhopadhyay, V. Viswanath, A. A. Iranmanesh, P. J. Wright, and P. Wesling. “WELCOME to ISQED 2016.” In Proceedings - International Symposium on Quality Electronic Design, ISQED, 2016-May:1, 2016. https://doi.org/10.1109/ISQED.2016.7479143.

Yang, C., B. Liu, Y. Wang, Y. Chen, H. Li, X. Zhang, and G. Sun. “The applications of NVM technology in hardware security.” In Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, 18-20-May-2016:311–16, 2016. https://doi.org/10.1145/2902961.2903043.

Liu, X., M. Mao, B. Liu, B. Li, Y. Wang, H. Jiang, M. Barnell, et al. “Harmonica: A Framework of Heterogeneous Computing Systems with Memristor-Based Neuromorphic Computing Accelerators.” IEEE Transactions on Circuits and Systems I: Regular Papers 63, no. 5 (May 1, 2016): 617–28. https://doi.org/10.1109/TCSI.2016.2529279.

Mao, F., Y. C. Chen, W. Zhang, H. Li, and B. He. “Library-based placement and routing in FPGAs with support of partial reconfiguration.” ACM Transactions on Design Automation of Electronic Systems 21, no. 4 (May 1, 2016). https://doi.org/10.1145/2901295.

Duan, S., Z. Dong, X. Hu, L. Wang, and H. Li. “Small-world Hopfield neural networks with weight salience priority and memristor synapses for digit recognition.” Neural Computing and Applications 27, no. 4 (May 1, 2016): 837–44. https://doi.org/10.1007/s00521-015-1899-7.

Wen, W., M. Mao, H. Li, Y. Chen, Y. Pei, and N. Ge. “A holistic tri-region MLC STT-RAM design with combined performance, energy, and reliability optimizations.” In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 1285–90, 2016. https://doi.org/10.3850/9783981537079_0917.

Wang, X., M. Mao, E. Eken, W. Wen, H. Li, and Y. Chen. “Sliding Basket: An adaptive ECC scheme for runtime write failure suppression of STT-RAM cache.” In Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, 762–67, 2016. https://doi.org/10.3850/9783981537079_0419.

Liu, B., X. Liu, C. Liu, W. Wen, M. Meng, H. Li, and Y. Chen. “Hardware acceleration for neuromorphic computing: An evolving view.” In 2015 15th Non-Volatile Memory Technology Symposium, NVMTS 2015, 2016. https://doi.org/10.1109/NVMTS.2015.7457496.

Sun, Z., X. Bi, W. Wu, S. Yoo, and H. H. Li. “Array Organization and Data Management Exploration in Racetrack Memory.” IEEE Transactions on Computers 65, no. 4 (April 1, 2016): 1041–54. https://doi.org/10.1109/TC.2014.2360545.

Nixon, K. W., X. Chen, and Y. Chen. “Footfall-GPS polling scheduler for power saving on wearable devices.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25-28-January-2016:563–68, 2016. https://doi.org/10.1109/ASPDAC.2016.7428071.

Zhang, X., S. Guangyu, Y. Zhang, Y. Chen, H. Li, W. Wen, and J. Di. “A novel PUF based on cell error rate distribution of STT-RAM.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25-28-January-2016:342–47, 2016. https://doi.org/10.1109/ASPDAC.2016.7428035.

Wu, C. R., W. Wen, T. Y. Ho, and Y. Chen. “Thermal optimization for memristor-based hybrid neuromorphic computing systems.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25-28-January-2016:274–79, 2016. https://doi.org/10.1109/ASPDAC.2016.7428023.

Nixon, K. W., X. Chen, Z. H. Mao, and Y. Chen. “SlowMo-enhancing mobile gesture-based authentication schemes via sampling rate optimization.” In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, 25-28-January-2016:462–67, 2016. https://doi.org/10.1109/ASPDAC.2016.7428055.

Yang, J., P. Wang, Y. Zhang, Y. Cheng, W. Zhao, Y. Chen, and H. H. Li. “Radiation-induced soft error analysis of STT-MRAM: A device to circuit approach.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 3 (March 1, 2016): 380–93. https://doi.org/10.1109/TCAD.2015.2474366.

Li, H., X. Bi, and Z. Sun. “The evolutionary spintronic technologies and their usage in high performance computing.” In International System on Chip Conference, 2016-February:350–55, 2016. https://doi.org/10.1109/SOCC.2015.7406981.

Chen, X., J. Mao, K. W. Nixon, and Y. Chen. “MORPh: Mobile OLED power friendly camera system.” In Proceedings of the 2016 27th International Symposium on Rapid System Prototyping: Shortening the Path from Specification to Prototype, RSP 2016, 7–11, 2016. https://doi.org/10.1145/2990299.2990302.