Publications

Liu, C., F. Liu, and H. Li. “Brain-inspired computing accelerated by memristor technology.” In Proceedings of the 4th ACM International Conference on Nanoscale Computing and Communication, NanoCom 2017, 2017. https://doi.org/10.1145/3109453.3123960.

Mao, M., W. Wen, Y. Zhang, Y. Chen, and H. Li. “An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.” IEEE Transactions on Computers 66, no. 9 (September 1, 2017): 1478–90. https://doi.org/10.1109/TC.2017.2690855.

Hu, M., Y. Chen, J. J. Yang, Y. Wang, and H. Li. “A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 8 (August 1, 2017): 1353–66. https://doi.org/10.1109/TCAD.2016.2618866.

Guo, J., W. Wen, J. Hu, D. Wang, H. Li, and Y. Chen. “FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1167–80. https://doi.org/10.1109/TCAD.2016.2619480.

Zhang, Y., B. Yan, X. Wang, and Y. Chen. “Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design.” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, no. 7 (July 1, 2017): 1181–92. https://doi.org/10.1109/TCAD.2016.2619484.

Li, S., W. Wen, Y. Wang, S. Han, Y. Chen, and H. H. Li. “An FPGA design framework for CNN sparsification and acceleration.” In Proceedings - IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2017, 28, 2017. https://doi.org/10.1109/FCCM.2017.21.

Niu, D., R. Xue, T. Cai, H. Li, K. Effah, and H. Zhang. “The new large-scale RNNLM system based on distributed neuron.” In Proceedings - 2017 IEEE 31st International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2017, 433–36, 2017. https://doi.org/10.1109/IPDPSW.2017.21.

Hassan, A. M., H. H. Li, and Y. Chen. “Hardware implementation of echo state networks using memristor double crossbar arrays.” In Proceedings of the International Joint Conference on Neural Networks, 2017-May:2171–77, 2017. https://doi.org/10.1109/IJCNN.2017.7966118.

Pan, C., M. Xie, Y. Liu, Y. Wang, C. J. Xue, Y. Chen, and J. Hu. “A lightweight progress maximization scheduler for non-volatile processor under unstable energy harvesting.” In ACM SIGPLAN Notices, 52:101–10, 2017. https://doi.org/10.1145/3078633.3081038.

Liu, C., M. Hu, J. P. Strachan, and H. H. Li. “Rescuing Memristor-based Neuromorphic Design with High Defects.” In Proceedings - Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062310.

Wang, Y., W. Wen, B. Liu, D. Chiarulli, and H. H. Li. “Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks.” In Proceedings - Design Automation Conference, Vol. Part 128280, 2017. https://doi.org/10.1145/3061639.3062256.

Eken, E., I. Bayram, Y. Zhang, B. Yan, H. Li, and Y. Chen. “Giant Spin-Hall assisted STT-RAM and logic design.” Integration, the VLSI Journal 58 (June 1, 2017): 253–61. https://doi.org/10.1016/j.vlsi.2017.04.002.

Chen, Y., H. H. Li, I. Bayram, and E. Eken. “Recent Technology Advances of Emerging Memories.” IEEE Design and Test 34, no. 3 (June 1, 2017): 8–22. https://doi.org/10.1109/MDAT.2017.2685381.

Bi, X., M. Mao, D. Wang, and H. Li. “Cross-layer optimization for multilevel cell STT-RAM caches.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 6 (June 1, 2017): 1807–20. https://doi.org/10.1109/TVLSI.2017.2665543.

Chen, Y., T. W. Kuo, and B. De Salvo. “Guest Editors' Introduction: Critical and Enabling Techniques for Emerging Memories.” IEEE Design and Test 34, no. 3 (June 1, 2017): 6–7. https://doi.org/10.1109/MDAT.2017.2682253.

Li, Z., C. Liu, H. Li, and Y. Chen. “Neuromorphic Hardware Acceleration Enabled by Emerging Technologies.” In Emerging Technology and Architecture for Big-Data Analytics. Springer, 2017.

Mao, J., X. Chen, K. W. Nixon, C. Krieger, and Y. Chen. “MoDNN: Local distributed mobile computing system for Deep Neural Network.” In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 1396–1401, 2017. https://doi.org/10.23919/DATE.2017.7927211.

Hassan, A. M., C. Yang, C. Liu, H. Li, and Y. Chen. “Hybrid spiking-based multi-layered self-learning neuromorphic system based on memristor crossbar arrays.” In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 776–81, 2017. https://doi.org/10.23919/DATE.2017.7927094.

Cheng, H. P., W. Wen, C. Wu, S. Li, H. Li, and Y. Chen. “Understanding the design of IBM neurosynaptic system and its tradeoffs: A user perspective.” In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 139–44, 2017. https://doi.org/10.23919/DATE.2017.7926972.

Chen, L., J. Li, Y. Chen, Q. Deng, J. Shen, X. Liang, and L. Jiang. “Accelerator-friendly neural-network training: Learning variations and defects in RRAM crossbar.” In Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, 19–24, 2017. https://doi.org/10.23919/DATE.2017.7926952.

Song, L., X. Qian, H. Li, and Y. Chen. “PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning.” In Proceedings - International Symposium on High-Performance Computer Architecture, 541–52, 2017. https://doi.org/10.1109/HPCA.2017.55.

Cline, B. T., S. Heinrich-Barna, P. J. Wright, H. Li, V. Viswanath, S. Hu, P. Wesling, G. Qu, S. Ghosh, and A. A. Iranmanesh. “Welcome.” In Proceedings - International Symposium on Quality Electronic Design, ISQED, 2017. https://doi.org/10.1109/ISQED.2017.7918277.

Chai, X., Z. Gan, Y. Lu, Y. Chen, and D. Han. “A novel image encryption algorithm based on the chaotic system and DNA computing.” International Journal of Modern Physics C 28, no. 5 (May 1, 2017). https://doi.org/10.1142/S0129183117500693.

Mohanty, S. P., X. Li, H. Li, and Y. Cao. “Guest Editorial Special Issue on Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing.” IEEE Transactions on Nanotechnology 16, no. 3 (May 1, 2017): 383–86. https://doi.org/10.1109/TNANO.2017.2680420.

Pan, C., M. Xie, C. Yang, Y. Chen, and J. Hu. “Exploiting multiple write modes of Nonvolatile main memory in embedded systems.” ACM Transactions on Embedded Computing Systems 16, no. 4 (May 1, 2017). https://doi.org/10.1145/3063130.