Publications

Found 600 results
[ Type(Desc)] Year
Conference Paper
F Chen, L Song, HH Li, and Y Chen. "PARC: A Processing-in-CAM Architecture for Genomic Long Read Pairwise Alignment using ReRAM." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 175-180. Vol. 2020-January. 2020.
S Li, E Hanson, H Li, and Y Chen. "PENNI: Pruned kernel sharing for efficient cnn inference." In 37th International Conference on Machine Learning, Icml 2020, 5819-5829. Vol. PartF168147-8. 2020.
S Zhang, H Li, and U Schlichtmann. "Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad. Vol. 2021-November. 2021.
N Inkawhich, KJ Liang, B Wang, M Inkawhich, L Carin, and Y Chen. "Perturbing across the feature hierarchy to improve standard and strict blackbox attack transferability." In Advances in Neural Information Processing Systems. Vol. 2020-December. 2020.
L Song, X Qian, H Li, and Y Chen. "PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning." In Proceedings International Symposium on High Performance Computer Architecture, 541-552. 2017.
A Li, C Wu, Y Chen, and B Ni. "Poster abstract: An efficient edge-assisted mobile system for video photorealistic style transfer." In Proceedings of the 4th Acm/Ieee Symposium on Edge Computing, Sec 2019, 332-333. 2019.
D Kang, Y Chen, and K Roy. "Power supply noise-aware scheduling and allocation for DSP synthesis." In Proceedings International Symposium on Quality Electronic Design, Isqed, 48-53. 2005.
Z Xie, H Ren, B Khailany, Y Sheng, S Santosh, J Hu, and Y Chen. "PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 13-18. Vol. 2020-January. 2020.
J Wang, Y Tim, WF Wong, and HH Li. "A practical low-power memristor-based analog neural branch predictor." In Proceedings of the International Symposium on Low Power Electronics and Design, 175-180. 2013.
X Chen, KW Nixon, and Y Chen. "Practical power consumption analysis with current smartphones." In International System on Chip Conference, 333-337. 2016.
M Mao, G Sun, Y Li, AK Jones, and Y Chen. "Prefetching techniques for STT-RAM based last-level cache in CMP systems." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 67-72. 2014.
Y Chen, K Roy, and CK Koh. "Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 894-899. 2004.
J Zhang, Y Chen, and H Li. "Privacy Leakage of Adversarial Training Models in Federated Learning Systems." In Ieee Computer Society Conference on Computer Vision and Pattern Recognition Workshops, 107-113. Vol. 2022-June. 2022.
B Wang, J Guo, A Li, Y Chen, and H Li. "Privacy-Preserving Representation Learning on Graphs: A Mutual Information Perspective." In Proceedings of the Acm Sigkdd International Conference on Knowledge Discovery and Data Mining, 1667-1676. 2021.
Y Chen, Y Zhang, and P Wang. "Probabilistic design in spintronic memory and logic circuit." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 323-328. 2012.
X Bi, Z Sun, H Li, and W Wu. "Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches." In Ieee/Acm International Conference on Computer Aided Design, Digest of Technical Papers, Iccad, 88-94. 2012.
F Chen, Z Li, W Kang, W Zhao, H Li, and Y Chen. "Process variation aware data management for magnetic skyrmions racetrack memory." In Proceedings of the Asia and South Pacific Design Automation Conference, Asp Dac, 221-226. Vol. 2018-January. 2018.
Z Sun, X Bi, and H Li. "Process variation aware data management for STT-RAM cache design." In Proceedings of the International Symposium on Low Power Electronics and Design, 179-184. 2012.
Y Chen, WF Wong, H Li, and CK Koh. "Processor caches built using multi-level spin-transfer torque RAM cells." In Proceedings of the International Symposium on Low Power Electronics and Design, 73-78. 2011.
W Wen, Y Zhang, Y Chen, Y Wang, and Y Xie. "PS3-RAM: A fast portable and scalable statistical STT-RAM reliability analysis method." In Proceedings Design Automation Conference, 1191-1196. 2012.
Z Chen, L Zhang, X Bi, and H Li. "A pseudo-weighted sensing scheme for memristor based cross-point memory." In Proceedings of the 2013 Ieee/Acm International Symposium on Nanoscale Architectures, Nanoarch 2013, 38-39. 2013.
H Jiang, K Yamada, Z Ren, T Kwok, F Luo, Q Yang, X Zhang, JJ Yang, Q Xia, Y Chen et al. "Pulse-Width Modulation based Dot-Product Engine for Neuromorphic Computing System using Memristor Crossbar Array." In Proceedings Ieee International Symposium on Circuits and Systems. Vol. 2018-May. 2018.
S Zhang, B Li, HH Li, and U Schlichtmann. "A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory Engines." In Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, Date 2020, 1426-1431. 2020.
X Chen, J Zheng, Y Chen, M Zhao, and CJ Xue. "Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices." In Proceedings Design Automation Conference, 1000-1005. 2012.
C Zhang, G Sun, W Zhang, F Mi, H Li, and W Zhao. "Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power." In 20th Asia and South Pacific Design Automation Conference, Asp Dac 2015, 100-105. 2015.

Pages