State-restrict MLC stt-ram designs for high-reliable high-performance memory system

TitleState-restrict MLC stt-ram designs for high-reliable high-performance memory system
Publication TypeConference Paper
Year of Publication2014
AuthorsW Wen, Y Zhang, M Mao, and Y Chen
Conference NameProceedings Design Automation Conference
Date Published01/2014

Multi-level Cell Spin-Transfer Torque Random AccessMemory (MLC STT-RAM) is a promising nonvolatile memory technology for highcapacity and high-performance applications. However, the reliability concerns and the complicated access mechanism greatly hinder the application of MLC STT-RAM. In this work, we develop a holistic solution set, namely, state-restrict MLC STT-RAM (SR-MLC STTRAM) to improve the data integrity and performance of MLC STTRAM with the minimized information density degradation. Three techniques: state restriction (StatRes), error pattern removal (ErrPR), and ternary coding (TerCode) are proposed at circuit level to reduce the read and write errors of MLC STT-RAMcells. State pre-recovery (PreREC) technique is also developed at architecture level to improve the access performance of SR-MLC STT-RAM by eliminating unnecessary two-step write operations. Our simulations show that compared to conventional MLC STT-RAM, SR-MLC STT-RAM can enhance the write and read reliability of memory cells by 10 - 10000×, allowing the application of simple error correction code schemes. Compared to single-level-cell (SLC) STT-RAM, SR-MLC STT-RAM based cache design can boost the system performance by 6.2% on average by leveraging the increased cache capacity at the same area and the improved write latency. Copyright 2014 ACM.