|Title||SPINBIS: Spintronics-based Bayesian inference system with stochastic computing|
|Publication Type||Journal Article|
|Year of Publication||2020|
|Authors||X Jia, J Yang, P Dai, R Liu, Y Chen, and W Zhao|
|Journal||Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems|
|Pagination||789 - 802|
Bayesian inference is an effective approach for solving statistical learning problems, especially with uncertainty and incompleteness. However, Bayesian inference is a computing-intensive task whose efficiency is physically limited by the bottlenecks of conventional computing platforms. In this paper, a spintronics-based stochastic computing (SC) approach is proposed for efficient Bayesian inference. The inherent stochastic switching behaviors of spintronic devices are exploited to build a stochastic bitstream generator (SBG) for SC with hybrid CMOS/magnetic tunnel junction (MTJ) circuits design. Aiming to improve the inference efficiency, an SBG sharing strategy is leveraged to reduce the required SBG array scale by integrating a switch network between SBG array and SC logic. A device-to-architecture level framework is proposed to evaluate the performance of spintronics-based Bayesian inference system (SPINBIS). Experimental results on data fusion applications have shown that SPINBIS could improve the energy efficiency about 12 × than MTJ-based approach with 45% design area overhead and about 26 × than FPGA-based approach.
|Short Title||Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems|