Read performance: The newest barrier in scaled stt-ram

TitleRead performance: The newest barrier in scaled stt-ram
Publication TypeJournal Article
Year of Publication2015
AuthorsY Zhang, Y Li, Z Sun, H Li, Y Chen, and AK Jones
JournalIeee Transactions on Very Large Scale Integration (Vlsi) Systems
Start Page1170
Pagination1170 - 1174
Date Published06/2015

Spin-torque transfer RAM (STT-RAM), a promising alternative to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling down to 45 nm and below, in particular, process variation, introduce the previously unreported and alarming trends in read performance and reliability due to reduced sensing margins and increasing error rates. In this brief, we study the scaling trends of STT-RAM from 65 down to 22 nm as they pertain to read performance, including a 50% increase in sensing versus peripheral circuit delay ratio and a more than 80% increase in uncorrectable read error rates. Through differential sensing, we show how 22 nm can return to sense delay ratio levels at 65 nm and uncorrectable read errors can be reduced by an order of magnitude. Through a case study of a multilevel STT-RAM cache, we show how a reconfigurable cache cell can create an extreme access mode (X-mode) based on differential sensing improve to outperform the state-of-The-art STT-RAM caching techniques in both raw performance and performance per watt by more than 10% while still reducing energy consumption over SRAM caches by more than 1/3.

Short TitleIeee Transactions on Very Large Scale Integration (Vlsi) Systems