|Title||PS3-RAM: A fast portable and scalable statistical STT-RAM reliability/energy analysis method|
|Publication Type||Journal Article|
|Year of Publication||2014|
|Authors||W Wen, Y Zhang, Y Chen, Y Wang, and Y Xie|
|Journal||Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems|
|Pagination||1644 - 1656|
The development of emerging spin-transfer torque random access memory (STT-RAM) is facing two major technical challenges-poor write reliability and high write energy, both of which are severely impacted by process variations and thermal fluctuations. The evaluations on STT-RAM design metrics and robustness often require a hybrid simulation flow, i.e., modeling the CMOS and magnetic devices with SPICE and macro-magnetic models, respectively. Very often, such a hybrid simulation flow involves expensive Monte Carlo simulations when the design and behavioral variabilities of STT-RAM are taken into account. In this paper, we propose a fast and scalable semi-analytical method-PS3-RAM, enabling efficient statistical simulations in STT-RAM designs. By eliminating the costly macro-magnetic and SPICE simulations, PS3-RAM achieves more than 100 000 × runtime speedup with excellent agreement with the result of conventional simulation method. PS3-RAM can also accurately estimate the STT-RAM write error rate and write energy distributions at both magnetic tunneling junction switching directions under different temperatures, demonstrating great potential in the analysis of STT-RAM reliability and write energy at the early design stage of memory or micro-architecture.
|Short Title||Ieee Transactions on Computer Aided Design of Integrated Circuits and Systems|