|Title||Multi-bit soft error tolerable L1 data cache based on characteristic of data value|
|Publication Type||Journal Article|
|Year of Publication||2015|
|Authors||DH Wang, HP Liu, and YR Chen|
|Journal||Journal of Central South University|
|Pagination||1769 - 1775|
Due to continuous decreasing feature size and increasing device density, on-chip caches have been becoming susceptible to single event upsets, which will result in multi-bit soft errors. The increasing rate of multi-bit errors could result in high risk of data corruption and even application program crashing. Traditionally, L1 D-caches have been protected from soft errors using simple parity to detect errors, and recover errors by reading correct data from L2 cache, which will induce performance penalty. This work proposes to exploit the redundancy based on the characteristic of data values. In the case of a small data value, the replica is stored in the upper half of the word. The replica of a big data value is stored in a dedicated cache line, which will sacrifice some capacity of the data cache. Experiment results show that the reliability of L1 D-cache has been improved by 65% at the cost of 1% in performance.
|Short Title||Journal of Central South University|