Modeling STT-RAM fabrication cost and impacts in NVSim

TitleModeling STT-RAM fabrication cost and impacts in NVSim
Publication TypeConference Paper
Year of Publication2017
AuthorsI Bayram, E Eken, D Kline, N Parshook, Y Chen, and AK Jones
Conference Name2016 7th International Green and Sustainable Computing Conference, Igsc 2016
Date Published04/2017
Abstract

Reducing power consumption of computational systems in the use-phase has become a significant focus to decrease thermal impacts and overall energy consumption of computing systems while having battery life benefits for increasingly mobile computing products. It is also a major driver of the sustainability of these systems due to the environmental impacts incurred through electricity generation. STT-RAM is a promising candidate to reduce use-phase power consumption due to its non-volatile data storage that dramatically reduces static power common in deeply scaled CMOS while maintaining high speed operation and excellent CMOS compatibility. However, augmenting CMOS chips with STT-RAM incurs an additional manufacturing cost through the extra materials and fabrication steps necessary to create the chip. In this paper we describe several extensions to the widely used NVSim tool that estimates area, performance, and use-phase power of STT-RAM to include calculations for manufacturing costs and environmental impacts such as energy usage, global warming potential, and other emissions. To demonstrate the value of these NVSim extensions, we provide a case study to experimentally determine the time it takes for replacing a SRAM cache with an ISO-capacity and ISO-area STT-RAM cache to overcome the manufacturing cost overhead. Our results indicate it can take an average of 80 and 160 days, respectively at 100% utilization to recover the manufacturing energy overhead.

DOI10.1109/IGCC.2016.7892599